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OMAP5910JZZG2 Datasheet(PDF) 65 Page - Texas Instruments |
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OMAP5910JZZG2 Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 171 page  Functional Overview 65 August 2002 -- Revised August 2004 SPRS197D 3.9 System DMA Controller The System Direct Memory Access (DMA) controller transfers data between points in the memory space without intervention by the MPU. The System DMA allows movements of data to and from internal memory, external memory, and peripherals to occur in the background of MPU operation. It is designed to off-load the block data transfer function from the MPU processor. The System DMA is configured by the MPU via the MPU private peripheral bus. The System DMA controller has nine independent general-purpose channels and seven ports that it may transfer to/from. An additional tenth channel is dedicated for use with the LCD controller. Of the seven available ports, the DMA transfers may occur between any two ports with the exception of the LCD port, which may only be used as a destination with the EMIFF or IMIF as the source. For maximum transfer efficiency, all nine channels are independent. This means that if multiple channels are exclusively accessing different ports, then simultaneous transfers performed by the channels will occur uninhibited. If the multiple channels are accessing common ports, however, some arbitration cycles will be necessary. Arbitration occurs in a round-robin fashion with configurable priority for each channel (high or low). The basic functional features of the system DMA controller are as follows: • Nine general-purpose and one dedicated (LCD) DMA channels • Round-robin arbitration scheme with programmable priorities • Concurrent DMA transfer capability • Start of transfer on peripheral request or host request • Byte-alignment and Byte-packing/unpacking capability • Burst transfer capability (IMIF, EMIFF, EMIFS, LCD, and Local ports) • Time-out counter for each DMA channel to prevent a channel locking on a memory location or peripheral. • Constant, post-incrementing, and Single- or Double-Indexed addressing modes • Autoinitialization for multiple block transfers without MPU intervention • Access available to all of the memory range (physical memory mapping and TIPB space) • Seven ports are available for different kinds of hardware resources. -- EMIFS port (allowing access to external asynchronous memory or devices) -- EMIFF port (allowing access to external SDRAM) -- IMIF port (allowing access to 192K bytes of shared SRAM) -- MPUI port (allowing access to DSP memory and peripherals) -- TIPB port (allowing peripheral register access) -- Local port (used for Host USB only) -- LCD port (allowing transfers to the LCD controller) • Memory-to-memory transfer granularity of 8, 16, and 32 bits. |
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