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OMAP5910JZZG2 Datasheet(PDF) 52 Page - Texas Instruments |
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OMAP5910JZZG2 Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 171 page  Functional Overview 52 August 2002 -- Revised August 2004 SPRS197D Table 3--5. DSP Public Peripheral Registers (Accessible via MPUI Port) MPU BASE ADDRESS REGISTER SET ACCESS WIDTH 0xE101 1800 McBSP1 Registers 16 0xE101 2000 MCSI2 Registers 16 0xE101 2800 MCSI1 Registers 16 0xE101 7000 McBSP3 Registers 16 Table 3--6. MPU Configuration Registers MPU BASE ADDRESS REGISTER SET ACCESS WIDTH 0xFFFB C800 MPU UART TIPB Bus Switch Registers 16 0xFFFE 0800 Ultra Low-Power Device (ULPD) Registers 16 0xFFFE 1000 OMAP5910 Configuration Registers 32 0xFFFE 1800 Device Die Identification Registers 32 0xFFFE C100 Local Bus Control Registers 32 0xFFFE C200 Local Bus MMU Registers 32 0xFFFE C900 MPU Interface (MPUI) Registers 32 0xFFFE CA00 TIPB (Private) Bridge 1 Configuration Registers 32 0xFFFE CC00 Traffic Controller Registers 32 0xFFFE CE00 MPU Clock/Reset/Power Control Registers 32 0xFFFE CF00 DPLL1 Configuration Registers 32 0xFFFE D200 DSP MMU Registers 32 0xFFFE D300 TIPB (Public) Bridge 2 Configuration Registers 16 0xFFFE D400 JTAG Identification Registers 32 3.3 DSP Memory Maps The DSP supports a unified program/data memory map (program and data accesses are made to the same physical space), however peripheral registers are located in a separate I/O space which is accessed via the DSP’s port instructions. 3.3.1 DSP Global Memory Map The DSP Subsystem contains 160K bytes of on-chip SRAM (64K bytes of DARAM and 96K bytes of SARAM). The MPU also has access to these memories via the MPUI (MPU Interface) port. The DSP also has access to the shared system SRAM (192K bytes) and both EMIF spaces (EMIFF and EMIFS) via the DSP Memory Management Unit (MMU) which is configured by the MPU. Table 3--7 shows the high-level program/data memory map for the DSP subsystem. DSP data accesses utilize 16-bit word addresses while DSP program fetches utilize byte addressing. Table 3--7. DSP Global Memory Map BYTE ADDRESS RANGE WORD ADDRESS RANGE INTERNAL MEMORY EXTERNAL MEMORY† 0x00 0000 -- 0x00 FFFF 0x00 0000 -- 0x00 7FFF DARAM 64K bytes 0x01 0000 -- 0x02 7FFF 0x00 8000 -- 0x01 3FFF SARAM 96K bytes 0x02 8000 -- 0x04 FFFF 0x01 4000 -- 0x02 7FFF Reserved 0x05 0000 -- 0xFF 7FFF 0x02 8000 -- 0x7F BFFF Managed by DSP MMU 0xFF 8000 -- 0xFF FFFF 0x7F C000 -- 0x7F FFFF PDROM (MPNMC = 0) Managed by DSP MMU (MPNMC =1) † This space could be external memory or internal shared system memory depending on the DSP MMU configuration. |
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