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LAN9500i-ABZJ-TR Datasheet(PDF) 42 Page - SMSC Corporation |
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LAN9500i-ABZJ-TR Datasheet(HTML) 42 Page - SMSC Corporation |
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42 / 66 page  USB 2.0 to 10/100 Ethernet Controller Datasheet Revision 1.1 (04-18-13) 42 SMSC LAN950x Family DATASHEET The Host Processor is connected to a Chipset containing the Host USB Controller (HC). The USB Host Controller interfaces to the device via the DP/DM USB signals. An Embedded Controller (EC) signals the Chipset and the Host processor to power up via an Enable signal. The EC interfaces to the device via four signals. The PME signal is an input to the EC from the device that indicates the occurrence of a wakeup event. The VBUS_DET output of the EC is used to indicate bus power availability. The PME_CLEAR (nRESET) signal is used to clear the PME. The PME_MODE_SEL signal is sampled by the device when PME_CLEAR (nRESET) is asserted and is used by the device to determine whether it should remain in PME mode or resume normal operation. GPIO pins are used for PME handling. The pins used depend on the value of the PHY_SEL pin, which determines PHY mode of operation. In Internal PHY mode of operation, GPIO0 is reserved for use as an output to signal the PME. GPIO1 is reserved for use as the PME_MODE_SEL input. GPIO8 and GPIO9 are reserved for analogous use, respectively, in External PHY mode of operation. The application scenario in Figure 6.1 assumes that the Host Processor and the Chipset are powered off, the EC is operational, and the device is in PME mode, waiting for a wake event to occur. A wake event will result in the device signaling a PME event to the EC, which will then wake up the Host Processor and Chipset via the Enable signal. The EC asserts VBUS_DET after the USB bus is powered, sets PME_MODE_SEL to determine whether the device is to begin normal operation or continue in PME mode, and asserts PME_CLEAR (nRESET) to clear the PME. The following wake events are supported: Wakeup Pin(s) The GPIO pins not reserved for PME handling have the capability to wake up the device when operating in PME mode. In order for a GPIO to generate a wake event, it’s enable bit must be set in the GPI010:8 Wakeup Enables or GPIO7:0 Wakeup Enables bytes of the EEPROM, as appropriate. During PME mode of operation, the GPIOs used for signaling (GPIOs 0 and 1 or GPIOs 8 and 9) are not affected by the values set in the corresponding bits of GPI010:8 Wakeup Enables or GPIO7:0 Wakeup Enables. GPIO10 is available as a wakeup pin in External PHY mode, while GPIOs 2 - 10 are available in Internal PHY Mode. The GPIO10 Detection Select bit in the GPIO PME Flags byte of the EEPROM sets the detection mode for GPIO10 in both External and Internal PHY mode (if set in GPI010:8 Wakeup Enables), while GPIOs 2 - 9 are fixed as active low when operating in Internal PHY mode. Magic Packet Reception of a Magic Packet when in PME mode will result in a PME being asserted. PHY Link Up Detection of a PHY link partner when in PME mode will result in a PME being asserted. In order to facilitate PME mode of operation, the GPIO PME Enable bit in the GPIO PME Flags field, must be set and all remaining GPIO PME Flags field bits must be appropriately configured for pulse or level signaling, buffer type, and GPIO PME WOL selection. The PME event is signaled on GPIO0 (External PHY mode) or GPIO8, depending on the PHY Mode of operation. The PME_MODE_SEL pin (GPIO1 in Internal Mode of operation, GPIO9 in External Mode of operation) must be driven to the value that determines whether or not the device remains in PME mode of operation (1) or resumes normal operation (0) when the PME is recognized and cleared by the EC via PME_CLEAR (nRESET) assertion. Note: When in PME mode, nRESET or POR will always cause the contents of the EEPROM to be reloaded. Note: GPIO10 may be used in PME and External PHY mode to connect to an external PHY’s Link LED, in order to generate a PHY Link Up wake event. |
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