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24LC22A-ISN Datasheet(PDF) 8 Page - Microchip Technology |
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24LC22A-ISN Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 24 page  24LC22A DS21683B-page 8 © 2007 Microchip Technology Inc. FIGURE 3-5: BUS TIMING START/STOP FIGURE 3-6: BUS TIMING DATA 3.1.6 SLAVE ADDRESS After generating a Start condition, the bus master trans- mits the slave address consisting of a 7-bit device code (1010000) for the 24LC22A. The eighth bit of slave address determines whether the master device wants to read or write to the 24LC22A (Figure 3-7). The 24LC22A monitors the bus for its corresponding slave address continuously. It generates an Acknowledge bit if the slave address was true and it is not in a programming mode. FIGURE 3-7: CONTROL BYTE ALLOCATION SCL SDA Start Stop VHYS TSU:STO THD:STA TSU:STA SCL SDA IN SDA OUT TSU:STA TSP TAA TF TLOW THIGH THD:STA THD:DAT TSU:DAT TSU:STO TBUF TAA TR Operation Slave Address R/W Read 1010000 1 Write 1010000 0 R/W A 10 1 0 0 0 0 Read/Write Start Slave Address |
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