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UCC2895DWTRG4 Datasheet(PDF) 4 Page - Texas Instruments |
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UCC2895DWTRG4 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 28 page  UCC1895, UCC2895, UCC3895 SLUS157P – DECEMBER 1999 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to +85°C for UCC2895x and TA = –55°C to +125°C for the UCC1895x. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT No-load comparator turn-off threshold 0.45 0.5 0.55 No-load comparator turn-on threshold 0.55 0.6 0.69 V No-load comparator hysteresis 0.035 0.1 0.165 OSCILLATOR fOSC Frequency TJ = 25°C 473 500 527 kHZ Frequency total variation( Over line, temperature 2.5% 5% VIH_SYNC SYNC input threshold, SYNC 2.05 2.1 2.4 VOH_SYNC High-level output voltage, SYNC ISYNC = –400 μA, VCT = 2.6 V 4.1 4.5 5 V VOL_SYNC Low-level output voltage, SYNC ISYNC = 100 μA, VCT = 0 V 0 0.5 1 Sync output pulse width LOADSYNC = 3.9 kΩ and 30 pF in parallel 85 135 ns VRT Timing resistor voltage 2.9 3 3.1 VCT(peak) Timing capacitor peak voltage 2.25 2.35 2.55 v VCT(valley) Timing capacitor valley voltage 0 0.2 0.4 CURRENT SENSE ICS(bias) Current sense bias current 0 V < CS < 2.5 V –4.5 20 µA 0 V ADS < 2.5 V Peak current threshold 1.9 2 2.1 V Overcurrent threshold 2.4 2.5 2.6 V Current sense to output delay 0 V ≤ CS ≤ 2.3 V 75 110 ns DELAB = DELCD = REF SOFT-START/SHUTDOWN ISOURCE Softstart source current SS/DISB = 3.0 V –40 –35 –30 µA CS = 1.9 V ISINK Softstart sink current SS/DISB = 3.0 V, 325 350 375 µA CS = 2.6 V Softstart/disable comparator 0.44 0.5 0.56 V threshold ADAPTIVE DELAY SET (ADS) DELAB/DELCD output voltage ADS = CS = 0 V 0.45 0.5 0.55 V ADS = 0 V 1.9 2 2.1 CS = 2 V tDELAY Output delay(2)(3) ADS = CS = 0 V 450 560 620 ns ADS bias current 0 V < ADS < 2.5 V –20 20 µA 0 V < CS < 2.5 V (2) Ensured by design. Not production tested. (3) Output delay is measured between OUTA and OUTB, or OUTC and OUTD. Output delay is defined as shown below where: tf(OUTA) = falling edge of OUTA signal, tr(OUTB) = rising edge of OUTB signal (see Figure 1 and Figure 2). 4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: UCC1895 UCC2895 UCC3895 |
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