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UCC2895-W Datasheet(PDF) 12 Page - Texas Instruments
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UCC2895-W Datasheet(HTML) 12 Page - Texas Instruments
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UCC1895, UCC2895, UCC3895
SLUS157P – DECEMBER 1999 – REVISED JUNE 2013
This pin combines two independent functions.
Disable Mode: A rapid shutdown of the chip is accomplished by externally forcing SS/DISB below 0.5 V,
externally forcing REF below 4 V, or if VDD drops below the undervoltage lockout threshold. In the case of REF
being pulled below 4 V or an undervoltage condition, SS/DISB is actively pulled to ground via an internal
If an overcurrent fault is sensed (CS = 2.5 V), a soft-stop is initiated. In this mode, SS/DISB sinks a constant
current of (10 × I
). The soft-stop continues until SS/DISB falls below 0.5 V. When any of these faults are
detected, all outputs are forced to ground immediately.
If SS/DISB is forced below 0.5 V, the pin starts to source current equal to I
. The only
time the part switches into low I
current mode, though, is when the part is in
Soft-start Mode: After a fault or disable condition has passed, VDD is above the start threshold, and, or,
SS/DISB falls below 0.5 V during a soft-stop, SS/DISB switches to a soft-start mode. The pin then sources
current, equal to I
. A user-selected resistor/capacitor combination on SS/DISB determines the soft start time
SS/DISB actively clamps the EAOUT pin voltage to approximately the SS/DISB pin
voltage during both soft-start, soft-stop, and disable conditions.
SYNC (Oscillator Synchronization)
This pin is bidirectional (refer to Figure 3). When used as an output, SYNC is used as a clock, which is the same
as the internal clock of the device. When used as an input, SYNC overrides the internal oscillator of the chip and
acts as the clock signal. This bidirectional feature allows synchronization of multiple power supplies. Also, the
SYNC signal internally discharge the C
capacitor and any filter capacitors that are present on the RAMP pin.
The internal SYNC circuitry is level sensitive, with an input-low threshold of 1.9 V, and an input-high threshold of
2.1 V. A resistor as small as 3.9 k
Ω may be tied between SYNC and GND to reduce the sync pulse width.
VDD (Chip Supply)
This is the input pin to the chip. VDD must be bypassed with a minimum of 1-
μF low ESR, low ESL capacitor to
ground. The addition of a 10-
μF low ESR, low ESL between VDD and PGND is recommended.
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