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UCC27525DGNR Datasheet(PDF) 6 Page - Texas Instruments |
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UCC27525DGNR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 41 page 10% 90% Enable Output Low High Low High Input tD1 tD2 UDG-11219 10% 90% Enable Output Low High Low High Input tD1 tD2 UDG-11220 10% 90% Enable Output Low High Low High Input tD3 tD4 UDG-11217 10% 90% Enable Output Low High Low High Input tD3 tD4 UDG-11218 UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 12 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal (unless otherwise noted,) PARAMETER TEST CONDITION MIN TYP MAX UNITS tR Rise time (3) CLOAD = 1.8 nF 7 18 tF Fall time(3) CLOAD = 1.8 nF 6 10 Delay matching between 2 INA = INB, OUTA and OUTB at 50% transition tM 1 4 channels point Minimum input pulse width ns tPW 15 25 that changes the output state Input to output propagation tD1, tD2 CLOAD = 1.8 nF, 5-V input pulse 6 13 23 delay (3) EN to output propagation tD3, tD4 CLOAD = 1.8 nF, 5-V enable pulse 6 13 23 delay (3) (3) See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4 Timing Diagrams Figure 1. Enable Function Figure 2. Enable Function (For Non-Inverting Input Driver Operation) (For Inverting Input Driver Operation) Figure 3. Non-Inverting Input Driver Operation Figure 4. Inverting Input Driver Operation 6 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: UCC27523, UCC27524, UCC27525, UCC27526 |
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