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ADM1232ARNZ1 Datasheet(PDF) 3 Page - Analog Devices

Part No. ADM1232ARNZ1
Description  Microprocessor Supervisory Circuit
Download  12 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM1232ARNZ1 Datasheet(HTML) 3 Page - Analog Devices

 
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ADM1232
Rev. C | Page 3 of
12
SPECIFICATIONS
VCC = full operating range, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TEMPERATURE
−40
+85
°C
TA = TMIN to TMAX.
POWER SUPPLY
Voltage
4.5
5.0
5.5
V
Current
20
50
μA
VIL, VIH = CMOS levels.
200
500
μA
VIL, VIH = TTL levels.
STROBE AND PB RESET INPUTS
Input High Level
2.0
VCC + 0.3
V
Input Low Level
−0.3
+0.8
V
INPUT LEAKAGE CURRENT
(STROBE, TOLERANCE)
−1.0
+1.0
μA
TD
1.6
μA
OUTPUT CURRENT
RESET
8
10
mA
VCC is at 4.5 V to 5.5 V.
RESET/RESET
−8
−12
mA
VCC is at 4.5 V to 5.5 V.
OUTPUT VOLTAGE
RESET/RESET
VCC − 0.5
VCC − 0.1
V
When sourcing less than 500 μA, RESET remains within
0.5 V of VCC on power-down until VCC drops below 2.0 V.
When sinking less than 500 μA, RESET remains within
0.5 V of GND on power-down until VCC drops below 2.0 V.
RESET/RESET High Level
0.4
V
RESET/RESET Low Level
2.4
V
1 V OPERATION
RESET Output Voltage
VCC − 0.1
V
When sourcing less than 50 μA.
RESET Output Voltage
0.1
V
When sinking less than 50 μA.
VCC TRIP POINT
5%
4.5
4.62
4.74
V
TOLERANCE = GND.
10%
4.25
4.37
4.49
V
TOLERANCE = VCC.
CAPACITANCE
Input (STROBE, TOLERANCE)
5
pF
TA = 25°C.
Output (RESET, RESET)
7
pF
TA = 25°C.
PB RESET
Time
20
ms
PB RESET must be held low for a minimum of 20 ms to
guarantee a reset.
Delay
1
4
20
ms
RESET ACTIVE TIME
250
610
1000
ms
STROBE
Pulse Width
70
ns
Timeout Period
62.5
150
250
ms
TD = 0 V.
250
600
1000
ms
TD = floating.
500
1200
2000
ms
TD = VCC.
VCC
Fall Time
10
μs
Guaranteed by design.
Rise Time
0
μs
Guaranteed by design.
VCC FAIL DETECT TO RESET
OUTPUT DELAY
RESET and RESET are logically correct.
50
μs
After VCC falls below the set tolerance voltage (see Figure 9).
250
610
1000
ms
After VCC rises above the set tolerance voltage.


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