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AD7490BCPZ-REEL7 Datasheet(PDF) 24 Page - Analog Devices |
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AD7490BCPZ-REEL7 Datasheet(HTML) 24 Page - Analog Devices |
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24 / 28 page  AD7490 Data Sheet Rev. D | Page 24 of 28 MICROPROCESSOR INTERFACING The serial interface on the AD7490 allows the part to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7490 with some of the more common microcontroller and DSP serial interface protocols. AD7490 to TMS320C541 The serial interface on the TMS320C541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7490. The CS input allows easy interfacing between the TMS320C541 and the AD7490 without any glue logic required. The serial port of the TMS320C541 is set up to operate in burst mode with internal CLKX0 (TX serial clock on Serial Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The connection diagram is shown in Figure 30. Note that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C541 provide equidistant sampling. The VDRIVE pin of the AD7490 takes the same supply voltage as that of the TMS320C541. This allows the ADC to operate at a higher voltage than the serial interface, that is, TMS320C541, if necessary. AD7490 TMS320C541* SCLK CLKX CLKR DR DT FSX FSR DOUT DIN CS *ADDITIONAL PINS REMOVED FOR CLARITY VDRIVE VDD Figure 30. Interfacing to the TMS320C541 AD7490 to ADSP-21xx The ADSP-21xx family of DSPs is interfaced directly to the AD7490 without any glue logic required. The VDRIVE pin of the AD7490 takes the same supply voltage as that of the ADSP- 218x.This allows the ADC to operate at a higher voltage than the serial interface, that is, ADSP-218x, if necessary. The SPORT0 control register should be set up as follows: • TFSW = RFSW = 1, alternate framing • INVRFS = INVTFS = 1, active low frame signal • DTYPE = 00, right justify data • SLEN = 1111, 16-bit data-words • ISCLK = 1, internal serial clock • TFSR = RFSR = 1, frame every word • IRFS = 0 • ITFS = 1 The connection diagram is shown in Figure 31. The ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode, and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS, and, as with all signal processing applications, equidistant sampling is necessary. In this example, however, the timer interrupt is used to control the sampling rate of the ADC, and under certain conditions, equidistant sampling may not be achieved. The timer register, for example, is loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and, thus, the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (that is, AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted or it may wait until the next clock edge. For example, if the ADSP-2189 with a 20 MHz crystal has an overall master clock frequency of 40 MHz, then the master cycle time is 25 ns. If the SCLKDIV register is loaded with a value of 3, an SCLK of 5 MHz is obtained, and eight master clock periods elapse for every 1 SCLK period. Depending on the throughput rate selected, if the timer registers are loaded with the value 803, 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling because the transmit instruc- tion occurs on a SCLK edge. If the number of SCLKs between interrupts is a figure of N, equidistant sampling is implemented by the DSP. AD7490 ADSP-218x* SCLK SCLK DR DT RFS TFS DOUT DIN CS *ADDITIONAL PINS REMOVED FOR CLARITY VDRIVE VDD Figure 31. Interfacing to the ADSP-218x AD7490 to DSP563xx The connection diagram in Figure 32 shows how the AD7490 can be connected to the ESSI (synchronous serial interface) of the DSP563xx family of DSPs from Motorola. Each ESSI (two on board) is operated in synchronous mode (the SYN bit in CRB = 1) with internally generated word length frame sync for both Tx and Rx (FSL1 = 0 and FSL0 = 0 in CRB). Normal operation of the ESSI is selected by making MOD = 0 in the CRB. |
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