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SST26VF064BA-104-5I-TD Datasheet(PDF) 8 Page - Microchip Technology |
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SST26VF064BA-104-5I-TD Datasheet(HTML) 8 Page - Microchip Technology |
8 / 76 page SST26VF064B / SST26VF064BA DS25119C-page 8 Advance Information 2013 Microchip Technology Inc. 4.3 Security ID SST26VF064B/064BA offer a 2 KByte Security ID (Sec ID) feature. The Security ID space is divided into two parts – one factory-programmed, 64-bit segment and one user-programmable segment. The factory-pro- grammed segment is programmed during manufactur- ing with a unique number and cannot be changed. The user-programmable segment is left unprogrammed for the customer to program as desired. Use the Program Security ID (PSID) command to pro- gram the Security ID using the address shown in Table 5-5. The Security ID can be locked using the Lockout Security ID (LSID) command. This prevents any future write operations to the Security ID. The factory-programmed portion of the Security ID can’t be programmed by the user; neither the factory- programmed nor user-programmable areas can be erased. 4.4 Hold Operation The HOLD# pin pauses active serial sequences with- out resetting the clocking sequence. This pin is active after every power up and only operates during SPI single-bit and dual-bit modes. Two factory configura- tions are available: SST26VF064B ships with the IOC bit set to ‘0’ and the HOLD# pin function enabled; SST26VF064BA ships with the IOC bit set to ‘1’ and the HOLD# pin function disabled. The HOLD# pin is always disabled in SQI mode and only works in SPI single-bit and dual-bit read mode. To activate the Hold mode, CE# must be in active low state. The Hold mode begins when the SCK active low state coincides with the falling edge of the HOLD# sig- nal. The Hold mode ends when the HOLD# signal’s ris- ing edge coincides with the SCK active low state. If the falling edge of the HOLD# signal does not coin- cide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD# signal does not coincide with the SCK active low state, then the device exits Hold mode when the SCK next reaches the active low state. See Figure 4-3. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high, and CE# must be driven active low. FIGURE 4-3: HOLD CONDITION WAVEFORM. TABLE 4-1: WRITE PROTECTION LOCK-DOWN STATES WP# IOC WPEN WPLD Execute WBPR Instruction Configuration Register L0 1 1 Not Allowed Protected L0 0 1 Not Allowed Writable L0 1 0 Not Allowed Protected L01 02 0 Allowed Writable H0 X 1 Not Allowed Writable H0 X 0 Allowed Writable X1 X 1 Not Allowed Writable X13 02 0 Allowed Writable 1. Default at power-up Register settings for SST26VF064B 2. Factory default setting is ‘0’. This is a non-volatile bit; default at power-up is the value set prior to power-down. 3. Default at power-up Register settings for SST26VF064BA Active Hold Active Hold Active 25119 F46.0 SCK HOLD# |
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