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SST26VF064BT-104-5I-SM Datasheet(PDF) 10 Page - Microchip Technology |
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SST26VF064BT-104-5I-SM Datasheet(HTML) 10 Page - Microchip Technology |
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10 / 76 page  SST26VF064B / SST26VF064BA DS25119C-page 10 Advance Information 2013 Microchip Technology Inc. 4.5.1 WRITE-ENABLE LATCH (WEL) The Write-Enable Latch (WEL) bit indicates the status of the internal memory’s Write-Enable Latch. If the WEL bit is set to ‘1’, the device is write enabled. If the bit is set to ‘0’ (reset), the device is not write enabled and does not accept any memory Program or Erase, Protection Register Write, or Lock-Down commands. The Write-Enable Latch bit is automatically reset under the following conditions: • Power-up • Reset • Write-Disable (WRDI) instruction completion • Page-Program instruction completion • Sector-Erase instruction completion • Block-Erase instruction completion • Chip-Erase instruction completion • Write-Block-Protection register instruction • Lock-Down Block-Protection register instruction • Program Security ID instruction completion • Lockout Security ID instruction completion • Write-Suspend instruction • SPI Quad Page program instruction completion • Write Status Register 4.5.2 WRITE SUSPEND ERASE STATUS (WSE) The Write Suspend-Erase status (WSE) indicates when an Erase operation has been suspended. The WSE bit is ‘1’ after the host issues a suspend command during an Erase operation. Once the suspended Erase resumes, the WSE bit is reset to ‘0’. 4.5.3 WRITE SUSPEND PROGRAM STATUS (WSP) The Write Suspend-Program status (WSP) bit indicates when a Program operation has been suspended. The WSP is ‘1’ after the host issues a suspend command during the Program operation. Once the suspended Program resumes, the WSP bit is reset to ‘0’. 4.5.4 WRITE PROTECTION LOCK-DOWN STATUS (WPLD) The Write Protection Lock-Down status (WPLD) bit indicates when the Block-Protection register is locked- down to prevent changes to the protection settings. The WPLD is ‘1’ after the host issues a Lock-Down Block-Protection command. After a power cycle, the WPLD bit is reset to ‘0’. 4.5.5 SECURITY ID STATUS (SEC) The Security ID Status (SEC) bit indicates when the Security ID space is locked to prevent a Write com- mand. The SEC is ‘1’ after the host issues a Lockout SID command. Once the host issues a Lockout SID command, the SEC bit can never be reset to ‘0.’ 4.5.6 BUSY The Busy bit determines whether there is an internal Erase or Program operation in progress. If the BUSY bit is ‘1’, the device is busy with an internal Erase or Program operation. If the bit is ‘0’, no Erase or Program operation is in progress. 4.5.7 CONFIGURATION REGISTER The Configuration register is a Read/Write register that stores a variety of configuration information. See Table 4-3 for the function of each bit in the register. TABLE 4-3: CONFIGURATION REGISTER Bit Name Function Default at Power-up Read/Write (R/W) 0 RES Reserved 0R 1 IOC I/O Configuration for SPI Mode 1 = WP# and HOLD# pins disabled 0 = WP# and HOLD# pins enabled 01 1. SST26VF064B default at Power-up is ‘0’ SST26VF064BA default at Power-up is ‘1’ R/W 2 RES Reserved 0R 3 BPNV Block-Protection Volatility State 1 = No memory block has been permanently locked 0 = Any block has been permanently locked 1R 4 RES Reserved 0R 5 RES Reserved 0R 6 RES Reserved 0R 7 WPEN Write-Protection Pin (WP#) Enable 1 = WP# enabled 0 = WP# disabled 02 2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down. R/W |
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