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SST25WF020AT-40-5I-NP Datasheet(PDF) 5 Page - Microchip Technology |
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SST25WF020AT-40-5I-NP Datasheet(HTML) 5 Page - Microchip Technology |
5 / 36 page 2013 Microchip Technology Inc. Preliminary DS21392A-page 5 SST25WF020A 4.0.1 HOLD In the hold mode, serial sequences underway with the SPI Flash memory are paused without resetting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD# mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The Hold mode ends when the rising edge of the HOLD# signal coincides with the SCK active low state. HOLD# must not rise or fall when SCK logic level is high. See Figure 4-2 for Hold Condi- tion waveform. Once the device enters Hold mode, SO will be in high- impedance state while SI and SCK can be VIL or VIH. If CE# is driven active high during a Hold condition, the device returns to standby mode. The device can then be re-initiated with the command sequences listed in Table 5-1. As long as HOLD# signal is low, the memory remains in the Hold condition. To resume communica- tion with the device, HOLD# must be driven active high, and CE# must be driven active low. See Figure 4-2 for Hold timing. FIGURE 4-2: HOLD CONDITION WAVEFORM 4.1 Write Protection SST25WF020A provides software Write protection. The Write Protect pin (WP#) enables or disables the lock- down function of the status register. The Block-Protec- tion bits (BP0, BP1, TB, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4-3 for the Block-Protection description. 4.1.1 WRITE PROTECT PIN (WP#) The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP# is driven low, the execution of the Write- Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4-1). When WP# is high, the lock-down function of the BPL bit is disabled. Active Hold Active 25139 F05.1 SCK HOLD# TABLE 4-1: CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION WP# BPL Execute WRSR Instruction L 1 Not Allowed L 0 Allowed H X Allowed |
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