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LCMXO2-256ZE-1SG32C Datasheet(PDF) 10 Page - Lattice Semiconductor |
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LCMXO2-256ZE-1SG32C Datasheet(HTML) 10 Page - Lattice Semiconductor |
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10 / 106 page  2-6 Architecture MachXO2 Family Data Sheet The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, etc. Internal logic can drive the global clock network for internally-generated global clocks and control signals. The maximum frequency for the primary clock network is shown in the MachXO2 External Switching Characteris- tics table. The primary clock signals for the MachXO2-256 and MachXO2-640 are generated from eight 17:1 muxes The available clock sources include eight I/O sources and 9 routing inputs. Primary clock signals for the MachXO2- 640U, MachXO2-1200/U and larger devices are generated from eight 27:1 muxes The available clock sources include eight I/O sources, 11 routing inputs, eight clock divider inputs and up to eight sysCLOCK PLL outputs. Figure 2-5. Primary Clocks for MachXO2 Devices 811 Primary Clock 0 Primary Clock 1 Primary Clock 2 Primary Clock 3 Primary Clock 4 Primary Clock 5 Primary Clock 6 8 Primary clocks for MachXO2-640U, MachXO2-1200/U and larger devices. Note: MachXO2-640 and smaller devices do not have inputs from the Edge Clock Divider or PLL and fewer routing inputs. These devices have 17:1 muxes instead of 27:1 muxes. Primary Clock 7 Dynamic Clock Enable Dynamic Clock Enable Dynamic Clock Enable Dynamic Clock Enable Dynamic Clock Enable 27:1 27:1 27:1 27:1 27:1 27:1 27:1 27:1 27:1 27:1 Up to 8 Dynamic Clock Enable Dynamic Clock Enable Dynamic Clock Enable Clock Switch Clock Switch |
Similar Part No. - LCMXO2-256ZE-1SG32C |
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Similar Description - LCMXO2-256ZE-1SG32C |
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