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TUSB8040A1 Datasheet(PDF) 31 Page - Texas Instruments |
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TUSB8040A1 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 38 page  TUSB8040A1 www.ti.com SLLSEE5A – FEBRUARY 2013 – REVISED MAY 2013 5 POWER UP AND RESET The TUSB8040A1 does not have specific power sequencing requirements with respect to the core power (VDD) or I/O and analog power (VDD33). The core power (VDD) or I/O power (VDD33) may be powered up for an indefinite period of time while the other is not powered up if all of these constraints are met: • All maximum ratings and recommended operating conditions are observed. • All warnings about exposure to maximum rated and recommended conditions are observed, particularly junction temperature. These apply to power transitions as well as normal operation. • Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the device. • Bus contention while VDD33 is powered down may violate the absolute maximum ratings. A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that range, either stable or in transition. A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay supervisory device or using an RC circuit. A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that range, either stable or in transition. A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay supervisory device or using an RC circuit. Copyright © 2013, Texas Instruments Incorporated POWER UP AND RESET 31 Submit Documentation Feedback Product Folder Links: TUSB8040A1 |
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