V

CCAD

V

SSAD

V

REFLO

V

REFHI

www.ti.com

Circuit Design and Layout Requirement

2.2

Power and Reference Voltage

V

conversion. V

current in the digital and core area can also follow through this V

100 nF decoupling capacitor should be placed between V

ground plane as shown in Figure 5.

V

noise on these two pins leads to random noise on the conversion result. With synchronized noise (with the

clock inside the device) presenting on these two pins, the conversion result looks

‘stable’ but has offset

and gain errors. A minimum 100 nF decoupling capacitor should be placed between them before they

reach the power and ground plane as shown in Figure 5. Do not share VIAs between V

or between V

voltage reference pins.

Figure 5. Power and Reference Voltage Layout Strategy

2.3

Input Channel

A typical input stage of the ADC input includes a low-pass filter and an operational amplifier (OP-AMP) as

shown in Figure 6. You can combine the low-pass filter and OP-AMP together.

Figure 6. ADC Input Strategy

2.3.1

Anti-aliasing Low-Pass Filter

Usually, the analog input carries all kinds of noise (FM noise, cell phone band noise and other spurious

signal). You should have some prior understanding of the nature of the input signals to be measured, for

example, the minimum or maximum frequency. Then, a filter can be designed to improve the signal to

noise ratio (SNR).

On the other side, the highest ADC sampling rate on TMS570LS31x/21x and RM4 devices is around 1

MSPS. The Nyquist frequency is half the sampling frequency. Any signal or noise beyond the Nyquist

frequency can be considered as

‘disturbance’ to the system and should be filtered before sampling.

To protect the analog input signal integrity, the capacitor and inductor used in the filter must be screened

carefully. The capacitance of the capacitor must not change across the voltage, frequency and

temperature range (NPO capacitor). The inductance of the inductor must not change across the current,

frequency and temperature range either. The change of capacitance or inductance will result in harmonic

distortion to the system and degradation of the ENOB.

5

SPNA140

– February 2012

Interfacing the Embedded 12-Bit ADC in a TMS570LS31x/21x and RM4x Series

Microcontrollers

Submit Documentation Feedback

Copyright

© 2012, Texas Instruments Incorporated