Block Diagram

2

Pin Configuration & Marking Information

,

Power Analog Microelectronics Inc

www.poweranalog.com

PAM2303

3A Low Noise Step-Down DC-DC Converter

EN

R1

R2

FB

+

-

IAMP

+

-

IRCMP

SW

PGND

SYNCHRONOUS

RECTIFIER NCH

(

)

MAIN

SWITCH PCH

(

)

PVIN

COMP

VIN

SHUTDOWN

OSC

RS LATCH

0.6VREF

FREQ

SHIFT

-

+

EA

S Q

R Q

SWITCHING

LOGIC

AND

BLANKING

CIRCUIT

SLOPE

COMP

1.5M

OSC

ANTI

SHOOT

THRU

-

-

TEST

VIN

GND

11/2011 Rev1.2

Top View

SOP-8(EP)

1

2

3

4

8

7

6

5

P2303B

XXXYW

A/B:

Y:

Year

W: Week

X:

Internal Code

Pin Configuration

Name

QFN3X3-16

SOP-8(EP)

Function

PGND

1,2,3

2

Main power ground pin

FB

4

3

Feedback voltage to internal error amplifier, the threshold voltage is 0.6V.

GND

5

4

Signal ground for small signal components.

NC

6,16

-

No connected

EN

7

5

Enable control input. Force this pin voltage above 1.5V, enables the chip,

and below 0.3V shuts down the device.

Test

8

6

Test mode. “

Low”connection is recommended.

VIN

9

7

Bias supply. Chip main power supply pin

PVIN

10,11,12

8

Input supply for power stage. Must be closely decoupled to PGND

SW

13,14,15

1

The drains of the internal main and synchronous power MOSFET.

Pin Description

12

11

10

9

13

14

15

16

1

2

3

4

8

7

6

5

FB

PGND

PGND

PGND

PVIN

PVIN

VIN

PVIN

P2303A

XXXYW

Top View

QFN 3X3-16