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NCP1252CDR2G Datasheet(PDF) 11 Page - ON Semiconductor |
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NCP1252CDR2G Datasheet(HTML) 11 Page - ON Semiconductor |
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11 / 18 page  NCP1252 http://onsemi.com 11 FB level Time Normal Operation: Skip: DC = 0% Figure 29. Mode of Operation versus the FB Pin Level DCmin < DC < DCmaxA/B/C VFBOL = 6.0 V Vf = 0.75 V Vskip = 0.3 V Operation @ Ton_min DC = DCmin Startup Sequence: The startup sequence is activated when Vcc pin reaches VCC(on) level. Once the startup sequence has been activated the internal delay timer (SSdelay) runs. Only when the internal delay elapses the soft start can be allowed if the BO pin level is above VBO level. If the BO pin threshold is reached or as soon as this level will be reached the soft start is allowed. When the soft start is allowed the SS pin is released from the ground and the current source connected to this pin sources its current to the external capacitor connected on SS pin. The voltage variation of the SS pin divided by 4 gives the same peak current variation on the CS pin. The following figures illustrate the different startup cases. Time BO pin Time SS pin Time DRV pin Time 120 ms: Internal delay Time BO pin Time SS pin Time DRV pin Time 120 ms: Internal delay CASE #1 CASE #2 Soft start Soft start No pulse Figure 30. Different Startup Sequence Case #1 & #2 VBO VCC(on) VCC pin VCC pin VBO VCC(on) With the Case #1, when the VCC pin reaches the VCC(on) level, the internal timer starts. As the BO pin level is above the VBO threshold at the end of the internal delay, a soft start sequence is started. With the Case #2, at the end of the internal delay, the BO pin level is below the VBO threshold thus the soft start sequence can not start. A new soft start sequence will start only when the BO pin reaches the VBO threshold. |
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