ADRF6518-EVALZ datasheet(4/36 Pages) AD

Part #	ADRF6518-EVALZ

Description	63 MHz Dual Programmable Filters and Variable Gain Amplifiers

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ADRF6518

Preliminary Technical Data

Rev. PrA | Page 4 of 36

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

NOISE/DISTORTION

Corner Frequency = 31 MHz

Output Noise Density

Maximum gain at fC/2

−105.5

dBV/Hz

Minimum gain at fC/2

−105.5

dBV/Hz

Second Harmonic, HD2

10 MHz fundamental, 1.5 V p-p at VGA1 output

voltage

VGA2, VGA3 at minimum gain (digital and

analog)

66

dBc

Third Harmonic, HD3

10 MHz fundamental, 1.5 V p-p at VGA1 output

voltage

VGA2, VGA3 at minimum gain (digital and

analog)

66

dBc

IMD3

f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite

output voltage

65

dBc

Corner Frequency = 63 MHz

Output Noise Density

Minimum gain

−105.5

dBV/Hz

Maximum gain

−105.5

dBV/Hz

Second Harmonic, HD2

20 MHz fundamental, 1.5 V p-p at VGA1 output

voltage

VGA2, VGA3 at minimum gain (digital and

analog)

56

dBc

Third Harmonic, HD3

20 MHz fundamental, 1.5 V p-p at VGA1 output

voltage

VGA2, VGA3 at minimum gain (digital and

analog)

66

dBc

DIGITAL LOGIC

LE, CLK, DATA, SDO

Input High Voltage, VINH

>2

V

Input Low Voltage, VINL

<0.8

V

Input Current, IINH/IINL

<1

µA

Input Capacitance, CIN

2

pF

SPI TIMING

LE, CLK, DATA, SDO

fSCLK

1/tSCLK

20

MHz

tDH

DATA hold time

5

ns

tDS

DATA setup time

5

ns

tLH

LE hold time

5

ns

tLS

LE setup time

5

ns

tPW

CLK high pulse width

5

ns

tD

CLK to SDO delay

5

ns

POWER AND ENABLE

VPS, VPSD, COM, COMD, ENBL

Supply Voltage Range

3.15

3.3

3.45

V

Total Supply Current

ENBL = 5 V

Maximum BW setting, high power filter

400

mA

Minimum BW setting, low power filter

360

mA

Filter Bypassed, high power mode

260

mA

Filter Bypassed, low power mode

230

mA

Disable Current

ENBL = 0 V

9

mA

Disable Threshold

1.6

V

Enable Response Time

Delay following ENBL low-to-high transition

20

µs

Disable Response Time

Delay following ENBL high-to-low transition

300

ns

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