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MT8VDDT3264AG-40BC4 Datasheet(PDF) 10 Page - Micron Technology

Part No. MT8VDDT3264AG-40BC4
Description  256MB, 512MB (x64, SR) 184-Pin DDR SDRAM UDIMM
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT8VDDT3264AG-40BC4 Datasheet(HTML) 10 Page - Micron Technology

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Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD8C32_64x64A.fm - Rev. J 8/08 EN
10
©2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB (x64, SR) 184-Pin DDR SDRAM UDIMM
Electrical Specifications
IDD Specifications
Table 9:
IDD Specifications and Conditions – 256MB (Die Revision ‘K’)
Values are shown for the
MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
Parameter/Condition
Symbol
-40B
-335
Units
Operating one bank active-precharge current: tRC = tRC (MIN); tCK = tCK
(MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
IDD0
800
720
mA
Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN);
tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock
cycle
IDD1
960
920
mA
Precharge power-down standby current: All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = LOW
IDD2P
32
32
mA
Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock cycle;
VIN =VREF for DQ, DM, and DQS
IDD2F
400
400
mA
Active power-down standby current: One device bank active; Power-down
mode; tCK = tCK (MIN); CKE = LOW
IDD3P
280
240
mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC
= tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per
clock cycle; Address and other control inputs changing once per clock cycle
IDD3N
480
440
mA
Operating burst read current: BL = 2; Continuous burst reads; One device
bank active; Address and control inputs changing once per clock cycle; tCK = tCK
(MIN); IOUT =0mA
IDD4R
1,440
1,280
mA
Operating burst write current: BL = 2; Continuous burst writes; One device
bank active; Address and control inputs changing once per clock cycle; tCK = tCK
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W
1,440
1,280
mA
Auto refresh current
tREFC = tRC (MIN)
IDD5
1,280
1,280
mA
tREFC = 7.8125µs
IDD5A
48
48
mA
Self refresh current: CKE
≤ 0.2V
IDD632
32
mA
Operating bank interleave read current: Four device bank interleaving
reads; BL = 4 with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and
control inputs change only during active READ or WRITE commands
IDD7
2,320
2,160
mA


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