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DA82562EM Datasheet(PDF) 10 Page - Intel Corporation |
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DA82562EM Datasheet(HTML) 10 Page - Intel Corporation |
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10 / 40 page  82562ET — Networking Silicon 6 Datasheet 3.4 Clock Pins 3.5 Platform LAN Connect Interface Pins Pin Name Pin Number Type Description X1 46 I Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz crystal of 50 PPM or better. Otherwise, X1 is driven by an external metal- oxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. X2 47 O Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz crystal of 50 PPM or better. Pin Name Pin Number Type Description LAN_CLK 39 O LAN Connect Clock. The LAN Connect Clock is driven by the 82562ET on two frequencies depending on operation speed. When the 82562ET is in 100BASE-TX mode, LAN_CLK drives a 50 MHz clock. Otherwise, LAN_CLK drives a 5 MHz clock for 10BASE-T. The LAN_CLK does not stop during normal operation. LAN_ RSTSYNC 42 I Reset/Synchronize. This is a multiplexed pin and is driven by the Media Access Control (MAC) layer device. Its functions are: • Reset. When this pin is asserted beyond one LAN Connect clock period, the 82562ET uses this signal Reset. To ensure reset of the 82562ET, the Reset signal should remain active for at least 500 µseconds. • Synchronize. When this pin is activated synchronously, for only one LAN Connect clock period, it is used to synchronize the MAC and PHY on LAN Connect word boundaries. LAN_ TXD[2:0] 45, 44, 43 I LAN Connect Transmit Data. The LAN Connect transmit pins are used to transfer data from the MAC device to the 82562ET. These pins are used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. The pins should be fully synchronous to LAN_CLK. LAN_ RXD[2:0] 37, 35, 34 O LAN Connect Receive Data. The LAN Connect receive pins are used to transfer data from the 82562ET to the MAC device. These pins are used to move received data and real time control and management data. They also move out of band control data from the PHY to the MAC. These pins are synchronous to LAN_CLK. |
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