ADF4159

Data Sheet

Rev. B | Page 2 of 36

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 10

Reference Input Section............................................................. 10

RF Input Stage............................................................................. 10

RF INT Divider........................................................................... 10

25-Bit Fixed Modulus ................................................................ 10

INT, FRAC, and R Counter Relationship................................ 10

R Counter .................................................................................... 10

Phase Frequency Detector (PFD) and Charge Pump............ 11

MUXOUT and Lock Detect...................................................... 11

Input Shift Register..................................................................... 11

Program Modes .......................................................................... 11

Register Maps.................................................................................. 12

FRAC/INT Register (R0) Map.................................................. 14

LSB FRAC Register (R1) Map................................................... 15

R Divider Register (R2) Map .................................................... 16

Function Register (R3) Map...................................................... 18

Clock Register (R4) Map ........................................................... 20

Deviation Register (R5) Map.................................................... 21

Step Register (R6) Map.............................................................. 22

Delay Register (R7) Map ........................................................... 23

Applications Information .............................................................. 24

Initialization Sequence .............................................................. 24

RF Synthesizer Worked Example ............................................. 24

Reference Doubler...................................................................... 24

Cycle Slip Reduction for Faster Lock Times........................... 24

Modulation.................................................................................. 25

Waveform Generation ............................................................... 25

Waveform Deviations and Timing........................................... 26

Single Ramp Burst...................................................................... 26

Single Triangular Burst.............................................................. 26

Single Sawtooth Burst................................................................ 26

Sawtooth Ramp........................................................................... 26

Triangular Ramp ........................................................................ 26

FMCW Radar Ramp Settings Worked Example...................... 26

Activating the Ramp .................................................................. 27

Other Waveforms ....................................................................... 27

Ramp Complete Signal to MUXOUT ..................................... 30

Interrupt Modes and Frequency Readback ............................ 31

Fast Lock Mode .......................................................................... 32

Spur Mechanisms ....................................................................... 33

Filter Design Using ADIsimPLL .............................................. 33

PCB Design Guidelines for the Chip Scale Package.............. 33

Application of the ADF4159 in FMCW Radar........................... 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY

6/13—Rev. A to Rev. B

Changed PFD Antibacklash Pulse from 3 ns to 1 ns in Phase

Frequency Detector (PFD) and Charge Pump Section ............. 11

Changes to Charge Pump Current Setting Section and

Reference Doubler Section............................................................ 16

Changes to Negative Bleed Current Enable Section and Loss of

Lock (LOL) Section ........................................................................ 18

5/13—Revision A: Initial Version