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UCC28083D Datasheet(PDF) 4 Page - Texas Instruments

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Part No. UCC28083D
Description  8-PIN CURRENT MODE PUSH-PULL PWM CONTROLLERS WITH PROGRAMMABLE SLOPE COMPENSATION
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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UCC28083D Datasheet(HTML) 4 Page - Texas Instruments

 
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UCC28083, UCC28084, UCC28085, UCC28086
UCC38083, UCC38084, UCC38085, UCC38086
SLUS488E − SEPTEMBER 2002 − REVISED JULY 2009
4
www.ti.com
electrical characteristics over recommended operating virtual junction temperature range,
VDD = 10 V (See Note 1),1-µF capacitor from VDD to GND, RT = 165 kΩ, RF = 1 kΩ, CF = 220 pF,
RSET = 50 kΩ, TA = −40°C to 85°C for UCC2808x, TA = 0°C to 70°C for UCC3808x, TA = TJ
(unless otherwise noted)
current sense
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Gain
See Note 3
1.9
2.2
2.5
V/V
Maximum input signal voltage
CTRL = 5 V,
See Note 4
0.47
0.52
0.57
V
CS to output delay time
CTRL = 3.5 V,
0 mV
≤ CS ≤ 600 mV
100
200
ns
Source current
−200
nA
Sink current
CS = 0.5 V,
RT = 2.0 V,
See Note 5
3
7
12
mA
Overcurrent threshold voltage
0.70
0.75
0.80
V
CTRL to CS offset voltage
CS = 0 V, 25
°C
0.55
0.70
0.90
V
CTRL to CS offset voltage
CS = 0 V
0.37
0.70
1.10
V
pulse width modulation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Maximum duty cycle
Measured at OUTA or OUTB, See Note 7
48%
49%
50%
Minimum duty cycle
CTRL = 0 V
0%
output
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Low-level output voltage (OUTA or OUTB)
IOUT = 100 mA
0.5
1.0
V
High-level output voltage (OUTA or OUTB)
IOUT = −50 mA,
(VDD − VOUT), See Note 6
0.5
1.0
V
Rise time
CLOAD = 1 nF
25
60
ns
Fall time
CLOAD = 1 nF
25
60
ns
soft-start
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OUTA/OUTB soft-start interval time,
UCC38083/4
CTRL = 1.8 V,
CS = 0 V,
Duty cycle from 0 to full, See Note 8
1.3
3.5
8.5
ms
OUTA/OUTB soft-start interval time,
UCC38085/6
CTRL = 1.8 V,
CS = 0 V,
Duty cycle from 0 to full, See Note 8
30
75
110
µs
slope compensation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
IRAMP, peak
ISET, peak = 30 µA, Full duty cycle
125
150
175
µA
NOTE 1: For UCCx8083/5, set VDD above the start threshold before setting to 10 V.
NOTE 2: Measured at ISET pin.
NOTE 3: Gain is defined by A
+
DV
CTRL
DV
CS
, 0
≤ VCS ≤ 0.4 V.
NOTE 4: Measured at trip point of latch with CS ramped from 0.4 V to 0.6 V.
NOTE 5: This internal current sink on the CS pin is designed to discharge and external filter capacitor. It is not intended to be a dc sink path.
NOTE 6: Not 100% production tested. Ensured by design and also by the rise time test.
NOTE 7: For devices in PW package, parameter tested at wafer probe.
NOTE 8: Ensured by design.


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