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FDD6030L Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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FDD6030L Datasheet(HTML) 1 Page - Fairchild Semiconductor |
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1 / 6 page  FDD6030L Rev. A1 FDD6030L N-Channel Logic Level Enhancement Mode Field Effect Transistor Features • 50 A, 30 V. R DS(ON) = 0.0135 Ω @ VGS = 10 V R DS(ON) = 0.0200 Ω @ VGS = 4.5 V. • Low gate charge. • Fast switching speed. • Low Crss. ©1999 Fairchild Semiconductor Corporation July 1999 ADVANCE INFORMATION G S D TO-252 S D G Absolute Maximum Ratings TC=25 oC unless otherwise noted Symbol Parameter Ratings Units VDSS Drain-Source Voltage 30 V VGSS Gate-Source Voltage ±20 V ID Maximum Drain Current -Continuous (Note 1) 50 (Note 1a) 12 Maximum Drain Current -Pulsed 150 A Maximum Power Dissipation @ TC = 25 oC (Note 1) 60 TA = 25 oC (Note 1a) 3.2 PD TA = 25 oC (Note 1b) 1.3 W TJ, Tstg Operating and Storage Junction Temperature Range -55 to +150 °C Thermal Characteristics RθJC Thermal Resistance, Junction-to- Case (Note 1) 2.1 °C/W 39 °C/W RθJA Thermal Resistance, Junction-to- Ambient (Note 1a) (Note 1b) 96 °C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDD6030L FDD6030L 13’’ 16mm 2500 General Description These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as DC/DC converters and high efficiency switching circuits where fast switching, low in-line power loss, and resistance to transients are needed. |
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Similar Description - FDD6030L |
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