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LAN9312-NZW Datasheet(PDF) 69 Page - Microchip Technology |
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LAN9312-NZW Datasheet(HTML) 69 Page - Microchip Technology |
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69 / 460 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet SMSC LAN9312 69 Revision 2.0 (02-14-13) DATASHEET 6.4.3.1 Port Default Priority As detailed in Figure 6.5, the default priority is based on the ingress ports priority bits in its port VID value. The PVID table is read and written by using the Switch Engine VLAN Command Register (SWE_VLAN_CMD), Switch Engine VLAN Write Data Register (SWE_VLAN_WR_DATA), Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA), and Switch Engine VLAN Command Status Register (SWE_VLAN_CMD_STS). Refer to Section 14.5.3.8, on page 376 through Section 14.5.3.11, on page 379 for detailed VLAN register descriptions. 6.4.3.2 IP Precedence Based Priority The transmit priority queue can be chosen based on the Precedence bits of the IPv4 TOS octet. This is supported for tagged and non-tagged packets for both type field and length field encapsulations. The Precedence bits are the three most significant bits of the IPv4 TOS octet. 6.4.3.3 DIFFSERV Based Priority The transmit priority queue can be chosen based on the DIFFSERV usage of the IPv4 TOS or IPv6 Traffic Class octet. This is supported for tagged and non-tagged packets for both type field and length field encapsulations. The DIFFSERV table is used to determine the packet priority from the 6-bit Differentiated Services (DS) field. The DS field is defined as the six most significant bits of the IPv4 TOS octet or the IPv6 Traffic Class octet and is used as an index into the DIFFSERV table. The output of the DIFFSERV table is then used as the priority. This priority is then passed through the Traffic Class table to select the transmit priority queue. Note: The DIFFSERV table is not initialized upon reset or power-up. If DIFFSERV is enabled, then the full table must be initialized by the host. The DIFFSERV table is read and written by using the Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG), Switch Engine DIFFSERV Table Write Data Register (SWE_DIFFSERV_TBL_WR_DATA), Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA), and Switch Engine DIFFSERV Table Command Status Register (SWE_DIFFSERV_TBL_CMD_STS). Refer to Section 14.5.3.12, on page 380 through Section 14.5.3.15, on page 383 for detailed DIFFSERV register descriptions. 6.4.3.4 VLAN Priority As detailed in Figure 6.5, the transmit priority queue can be taken from the priority field of the VLAN tag. The VLAN priority is sent through a per port Priority Regeneration table, which is used to map the VLAN priority into a user defined priority. The Priority Regeneration table is programmed by using the Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII), Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1), and Switch Engine Port 2 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_2). Refer to Section 14.5.3.33, on page 403 through Section 14.5.3.35, on page 405 for detailed descriptions of these registers. |
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