Application Note

AN-1177

Rev. 0 | Page 5 of 12

DIFFERENTIAL SIGNALLING AND LVDS/M-LVDS

Differential transmission is communication where two

complementary signals are transmitted, with the received signal

comprising the difference between the two signal lines. This

form of communication, used by both LVDS and M-LVDS,

has two distinct advantages, high noise immunity and low

emissions.

The high noise immunity arises because typically a noise

source couples equally onto both signal lines, leaving the

differential signal unaffected. Emissions from differential

signaling are low due to the tight coupling between the two

complementary signal lines when using a typical medium

(twisted pair cable, or closely placed strip line).

DEFINITIONS AND OUTPUT LEVELS

For LVDS and M-LVDS, one signal line is noninverting (that is,

high for a Logic 1 and low for a Logic 0) and the other signal

line is inverting (that is, the complement of the noninverting

signal). The difference in voltage between the two signal lines

the magnitude of the differential voltage (positive or negative),

voltage swings around 0 V. Typical LVDS signal levels are

1.35V

1.05V

0V

LOGIC 0

LOGIC 1

LOGIC 1

0.3V

–0.3V

Figure 8. LVDS Output Levels

The differential voltage on an LVDS or M-LVDS bus is

generated by a driver current source. Noninverting LVDS driver

outputs or receiver inputs are generally denoted with a + and

inverting driver outputs or receiver inputs with a −.

Pin names are shown for the ADN4663 2-channel LVDS driver

and ADN4664 2-channel LVDS receiver in Figure 9. M-LVDS

follows the convention of RS-485 physical layer transceivers in

naming the bus lines A for the noninverting signal and B for the

inverting signal, or Y and Z for driver outputs on a full-duplex

transceiver.

ADN4663

GND

100Ω

100Ω

ADN4664

GND

Figure 9. ADN4663 and ADN4664 2-Channel LVDS Point-to-Point

The distinction between LVDS and M-LVDS and other

differential signaling standards is that they have a low output

swing. The differential output voltage and common mode range

specifications of LVDS and M-LVDS are shown in Figure 10. For

and a maximum of 450 mV with a load of 100 Ω. This allows

low power operation and ensures that while transitions are fast,

to allow high data rates, the reduced output swing means that

the slew rate is not too severe. Rise and fall times are generally

in the region of hundreds of picoseconds, resulting in slew rates

of around 0.5 V/ns to 2.5 V/ns.

250mV

450mV

480mV

650mV

M-LVDS

LVDS

MIN

MIN

MAX

MAX

0V TO

2.4V

–1V TO

3.4V

4V

3V

2V

1V

0V

–1V

M-LVDS

LVDS

Figure 10. LVDS and M-LVDS Signaling Levels

M-LVDS has slew-rate limited drivers to enhance the robustness

of the signaling when there are additional impedance

discontinuities from multiple drivers/receivers and stubs. This

means that M-LVDS is limited to lower data rates compared to

LVDS. The ADN4690E through ADN4697E are available with

options for 100 Mbps or higher speed 200 Mbps. Another

characteristic of M-LVDS is increased driver strength, resulting

maximum of 650 mV with a load of 50 Ω (two termination

resistors of 100 Ω, one either end of the bus).

RECEIVER THRESHOLDS

The receiver thresholds are the differential voltage levels above

or below which the received signal is considered a Logic 1 or a

Logic 0.