FAN5250

8

REV. 1.1.6 3/12/03

Output Voltage Programming

The output voltage of the converter is programmed by an

internal DAC in discrete steps between 0.6V and 1.75V:

Table 1. Output Voltage VID

1 = Logic High or open, 0 = Logic Low

VID0–4 pins will assume a logic 1 level if left open as each

has a 12µA internal current source pull-up to 2.5V. The

output of the DAC voltage also establishes the thresholds for

PGOOD, UVP and OVP thresholds.

Alternative Voltage Programming Input

The output voltage can alternatively be set by the ALTV pin.

This override of the VID DAC becomes necessary during

power-up and some power saving modes of operation, when

the voltage on the processor is insufficient to provide correct

VID codes to the controller. Therefore, the required core

voltage should be set by some means external to the

processor. A common approach to this problem is to provide

hard-wired VID codes via a multiplexer controlled by the

CPU. That approach lacks simplicity and takes many

external components and valuable motherboard area.

The FAN5250 uses a simpler way to set the core voltages

when the CPU is incapable of providing valid VID codes.

A resistor-MOSFET network (shown in Figure 4) works

with the calibrated 10µA current from the ALTV pin to set

the ALTV voltage when the MOSFET's gate is driven high.

The controller regulates the output voltage to the level

established on the ALTV pin when this voltage is lower than

the highest VID programmed voltage (1.75V). When both

MOSFET gates are low, the ALTV pin goes to 2.5V and the

output is controlled by the VID code. If a more accurate

Deep-Sleep (DSX) and Start voltages are required than the

internal current source can provide, it may be overridden

with the external resistor shown (grey-shading).

Figure 4. ALTV Programming

When relying on the internal current source to set ALTV:

When using Rx for greater accuracy, on the internal current

source to set ALTV, Choose a value for Rx where

VID4

VID3

VID2

VID1

VID0

CPU

11111

0.600

11110

0.625

11101

0.650

11100

0.675

11011

0.700

11010

0.725

11001

0.750

11000

0.775

10111

0.800

10110

0.825

10101

0.850

10100

0.875

10011

0.900

10010

0.925

10001

0.950

10000

0.975

01111

1.000

01110

1.050

01101

1.100

01100

1.150

01011

1.200

01010

1.250

01001

1.300

01000

1.350

00111

1.400

00110

1.450

00101

1.500

00100

1.550

00011

1.600

00010

1.650

00001

1.700

00000

1.750

START

DSX

ALTV

6

R8

R7

REF

Rx

2.5V

10?A

R7

V

START

10

µA

--------------------





=

and R8

⋅

V

DSX

10

µA

--------------





=

(4)

R7

VV

START

×

V

REF

V

START

–

R

X

10

µA

×

()

+

---------------------------------------------------------------------------------





=

R8

RV

START

×

V

REF

V

DSX

–

R

X

10

µA

×

()

+

--------------------------------------------------------------------------





=

V

REF

V

START

–

R

X

-----------------------------------------



 10

»

µA

(5)

, then