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W9751G6KB-25 Datasheet(PDF) 38 Page - Winbond

Part # W9751G6KB-25
Description  Double Data Rate architecture: two data transfers per clock cycle
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9751G6KB-25 Datasheet(HTML) 38 Page - Winbond

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W9751G6KB
Publication Release Date: Sep. 03, 2012
- 38 -
Revision A04
10.3 Recommended DC Operating Conditions
SYM.
PARAMETER
MIN.
TYP.
MAX.
UNIT
NOTES
VDD
Supply Voltage
1.7
1.8
1.9
V
1
VDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
5
VDDQ
Supply Voltage for Output
1.7
1.8
1.9
V
1, 5
VREF
Input Reference Voltage
0.49 x VDDQ
0.5 x VDDQ
0.51 x VDDQ
V
2, 3
VTT
Termination Voltage (System)
VREF - 0.04
VREF
VREF + 0.04
V
4
Notes:
1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ
must than or equal to VDD.
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF
is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
3. Peak to peak AC noise on VREF may not exceed
2 % VREF(dc).
4. VTT of transmitting device must track VREF of receiving device.
5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
10.4 ODT DC Electrical Characteristics
PARAMETER/CONDITION
SYM.
MIN.
NOM.
MAX.
UNIT
NOTES
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 Ω
Rtt1(eff)
60
75
90
Ω
1
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150
Ω
Rtt2(eff)
120
150
180
Ω
1
Rtt effective impedance value for EMRS(A6,A2)=1,1; 50
Ω
Rtt3(eff)
40
50
60
Ω
1, 2
Deviation of VM with respect to VDDQ/2
ΔVM
-6
+6
%
1
Notes:
1. Test condition for Rtt measurements.
2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
Measurement Definition for Rtt(eff):
Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I(VIL (ac))
respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18.
Rtt(eff) = (VIH(ac)
– VIL(ac)) /(I(VIHac) – I(VILac))
Measurement Definition for
ΔVM:
Measure voltage (VM) at test pin (midpoint) with no load.
ΔVM = ((2 x Vm / VDDQ) – 1) x 100%
10.5 Input DC Logic Level
PARAMETER
SYM.
MIN.
MAX.
UNIT
DC input logic HIGH
VIH(dc)
VREF + 0.125
VDDQ + 0.3
V
DC input logic LOW
VIL(dc)
-0.3
VREF - 0.125
V
10.6 Input AC Logic Level
PARAMETER
SYM.
-18
-25/25I/25A/25K/-3
UNIT
MIN.
MAX.
MIN.
MAX.
AC input logic HIGH
VIH (ac)
VREF + 0.200
VREF + 0.200
VDDQ + VPEAK
1
V
AC input logic LOW
VIL (ac)
VREF - 0.200
VSSQ - VPEAK
1
VREF - 0.200
V
Note:
1. Refer to the page 67 sections 10.14.1 and 10.14.2 AC Overshoot/Undershoot specification table for VPEAK value: maximum
peak amplitude allowed for Overshoot/Undershoot.


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