W631GG6KB12K datasheet(2/158 Pages) WINBOND

Part #	W631GG6KB12K

Description	Double Data Rate architecture: two data transfers per clock cycle

Download	158 Pages

Scroll/Zoom	100%

Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

Logo

2 / 158 page

W631GG6KB

Publication Release Date: Feb. 27, 2013

Revision A04

- 2 -

7.7.2

DLL ―off‖ to DLL ―on‖ Procedure.......................................................................................26

7.8

Input clock frequency change..............................................................................................................27

7.8.1

Frequency change during Self-Refresh............................................................................27

7.8.2

Frequency change during Precharge Power-down ..........................................................27

7.9

Write Leveling .....................................................................................................................................29

7.9.1

DRAM setting for write leveling & DRAM termination function in that mode ....................30

7.9.2

Write Leveling Procedure .................................................................................................30

7.9.3

Write Leveling Mode Exit .................................................................................................32

7.10

Multi Purpose Register ........................................................................................................................33

7.10.1

MPR Functional Description.............................................................................................34

7.10.2

MPR Register Address Definition.....................................................................................35

7.10.3

Relevant Timing Parameters............................................................................................35

7.10.4

Protocol Example .............................................................................................................35

7.11

ACTIVE Command..............................................................................................................................41

7.12

PRECHARGE Command ....................................................................................................................41

7.13

READ Operation .................................................................................................................................42

7.13.1

READ Burst Operation .....................................................................................................42

7.13.2

READ Timing Definitions..................................................................................................43

7.13.2.1

READ Timing; Clock to Data Strobe relationship....................................................44

7.13.2.2

READ Timing; Data Strobe to Data relationship .....................................................45

7.13.2.3

tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .............................................46

7.13.2.4

tRPRE Calculation..................................................................................................47

7.13.2.5

tRPST Calculation ..................................................................................................47

7.13.2.6

Burst Read Operation followed by a Precharge......................................................53

7.14

WRITE Operation................................................................................................................................55

7.14.1

DDR3 Burst Operation .....................................................................................................55

7.14.2

WRITE Timing Violations .................................................................................................55

7.14.2.1

Motivation ...............................................................................................................55

7.14.2.2

Data Setup and Hold Violations..............................................................................55

7.14.2.3

Strobe to Strobe and Strobe to Clock Violations.....................................................55

7.14.2.4

Write Timing Parameters ........................................................................................55

7.14.3

Write Data Mask...............................................................................................................56

7.14.4

tWPRE Calculation...........................................................................................................57

7.14.5

tWPST Calculation ...........................................................................................................57

7.15

Refresh Command ..............................................................................................................................64

7.16

Self-Refresh Operation .......................................................................................................................66

7.17

Power-Down Modes ............................................................................................................................68

7.17.1

Power-Down Entry and Exit .............................................................................................68

7.17.2

Power-Down clarifications - Case 1 .................................................................................74

7.17.3

Power-Down clarifications - Case 2 .................................................................................74

7.17.4

Power-Down clarifications - Case 3 .................................................................................75

7.18

ZQ Calibration Commands..................................................................................................................76

Similar Part No. - W631GG6KB12K

Manufacturer	Part #	Datasheet	Description
Winbond	W631GU6KB-12-TR	4Mb / 160P	8M ??8 BANKS ??16 BIT DDR3L SDRAM

More results

Similar Description - W631GG6KB12K

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G2IB4	832Kb / 50P	Double Data Rate architecture; two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9751G6KB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Elite Semiconductor Mem...	M13L2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

W631GG6KB12K Datasheet(PDF) 2 Page - Winbond

W631GG6KB12K Datasheet(HTML) 2 Page - Winbond

Similar Part No. - W631GG6KB12K

Similar Description - W631GG6KB12K

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL