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W9412G6JH-5 Datasheet(PDF) 26 Page - Winbond

Part # W9412G6JH-5
Description  Double Data Rate architecture; two data transfers per clock cycle
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9412G6JH-5 Datasheet(HTML) 26 Page - Winbond

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W9412G6JH
Publication Release Date: Nov. 29, 2011
- 26 -
Revision A03
9.6
AC Characteristics and Operating Condition
SYM.
PARAMETER
-4
-5/-5I/-5K
-6I
UNIT
NOTES
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
tRC
Active to Ref/Active Command Period
48
50
54
nS
tRFC
Ref to Ref/Active Command Period
60
70
70
tRAS
Active to Precharge Command Period
40
70000
40
70000
42
100000
tRCD
Active to Read/Write Command Delay Time
16
15
18
tRAP
Active to Read with Auto-precharge Enable
16
15
18
tCCD
Read/Write(a)
to
Read/Write(b)
Command
Period
1
1
1
tCK
tRP
Precharge to Active Command Period
16
15
18
nS
tRRD
Active(a) to Active(b) Command Period
12
10
12
tWR
Write Recovery Time
12
15
15
tDAL
Auto-precharge Write Recovery + Precharge
Time
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
18
tCK
CLK Cycle Time
CL = 2
-
-
7.5
12
7.5
12
nS
CL = 2.5
-
-
6
12
6
12
CL = 3
4
12
5
12
6
12
CL = 4
4
12
-
-
-
-
tAC
Data Access Time from CLK,
CLK
-0.65
0.65
-0.7
0.7
-0.7
0.7
16
tDQSCK
DQS Output Access Time from CLK,
CLK
-0.55
0.55
-0.6
0.6
-0.6
0.6
tDQSQ
Data Strobe Edge to Output Data Edge Skew
0.4
0.4
0.4
tCH
CLk High Level Width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
11
tCL
CLK Low Level Width
0.45
0.55
0.45
0.55
0.45
0.55
tHP
CLK Half Period (minimum of actual tCH, tCL)
min
(tCL,tCH)
min,
(tCL,tCH)
min,
(tCL,tCH)
nS
tQH
DQ Output Data Hold Time from DQS
tHP-0.5
tHP-0.5
tHP-0.5
tRPRE
DQS Read Preamble Time
0.9
1.1
0.9
1.1
0.9
1.1
tCK
11
tRPST
DQS Read Postamble Time
0.4
0.6
0.4
0.6
0.4
0.6
tDS
DQ and DM Setup Time
0.4
0.4
0.4
nS
tDH
DQ and DM Hold Time
0.4
0.4
0.4
tDIPW
DQ and DM Input Pulse Width (for each input)
1.75
1.75
1.75
tDQSH
DQS Input High Pulse Width
0.35
0.35
0.35
tCK
11
tDQSL
DQS Input Low Pulse Width
0.35
0.35
0.35
tDSS
DQS Falling Edge to CLK Setup Time
0.2
0.2
0.2
tDSH
DQS Falling Edge Hold Time from CLK
0.2
0.2
0.2
tWPRES
Clock to DQS Write Preamble Set-up Time
0
0
0
nS


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