Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

W9412G2IB4 Datasheet(PDF) 30 Page - Winbond

Part No. W9412G2IB4
Description  Double Data Rate architecture; two data transfers per clock cycle
Download  50 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9412G2IB4 Datasheet(HTML) 30 Page - Winbond

Back Button W9412G2IB4 Datasheet HTML 26Page - Winbond W9412G2IB4 Datasheet HTML 27Page - Winbond W9412G2IB4 Datasheet HTML 28Page - Winbond W9412G2IB4 Datasheet HTML 29Page - Winbond W9412G2IB4 Datasheet HTML 30Page - Winbond W9412G2IB4 Datasheet HTML 31Page - Winbond W9412G2IB4 Datasheet HTML 32Page - Winbond W9412G2IB4 Datasheet HTML 33Page - Winbond W9412G2IB4 Datasheet HTML 34Page - Winbond Next Button
Zoom Inzoom in Zoom Outzoom out
 30 / 50 page
background image
W9412G2IB
Publication Release Date: Aug. 30, 2010
- 30 -
Revision A06
V SWING (MAX)
VDDQ
VSS
T
T
VIH min (AC)
VREF
VIL max (AC)
SLEW = (VIHmin (AC) - VILmax (AC)) / T
Output
50 Ω
VTT
Timing Reference Load
Output
V(out)
30pF
Notes:
(1)
Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
(2)
All voltages are referenced to VSS, VSSQ. ( 2.5V
±0.1V for DDR500)
(3)
Peak to peak AC noise on VREF may not exceed
±2% VREF(DC).
(4)
VOH = 1.95V, VOL = 0.35V
(5)
VOH = 1.9V, VOL = 0.4V
(6)
The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V.
The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V.
(7)
These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values
of tCK and tRC.
(8)
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set
equal to VREF and must track variations in the DC level of VREF.
(9)
These parameters depend on the output loading. Specified values are obtained with the output open.
(10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed
slope.
(11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to
the nearest decimal place.
(i.e., tDQSS = 0.75
× tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.)
(12) VX is the differential clock cross point voltage where input timing measurement is referenced.
(13) VID is magnitude of the difference between CLK input level and CLK input level.
(14) VISO means {VICK(CLK)+VICK( CLK )}/2.
(15) Refer to the figure below.


Similar Part No. - W9412G2IB4

ManufacturerPart No.DatasheetDescription
Winbond
Winbond
W9412G2IB WINBOND-W9412G2IB Datasheet
832Kb / 50P
   1M 횞 4 BANKS 횞 32 BITS GDDR SDRAM
More results

Similar Description - W9412G2IB4

ManufacturerPart No.DatasheetDescription
Elite Semiconductor Memory Technology Inc.
Elite Semiconductor Mem...
M13S128324A-2M ESMT-M13S128324A-2M Datasheet
1Mb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
M13S2561616A-2S ESMT-M13S2561616A-2S Datasheet
1Mb / 49P
   Double-data-rate architecture, two data transfers per clock cycle
M13S5121632A-2S ESMT-M13S5121632A-2S Datasheet
705Kb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
Winbond
Winbond
W9412G6JH-5 WINBOND-W9412G6JH-5 Datasheet
1Mb / 53P
   Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Memory Technology Inc.
Elite Semiconductor Mem...
M13S2561616A-2A ESMT-M13S2561616A-2A Datasheet
1Mb / 49P
   Double-data-rate architecture, two data transfers per clock cycle
Winbond
Winbond
W9751G6KB-25 WINBOND-W9751G6KB-25 Datasheet
1Mb / 87P
   Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Memory Technology Inc.
Elite Semiconductor Mem...
M13L32321A-2G ESMT-M13L32321A-2G Datasheet
1Mb / 48P
   Double-data-rate architecture, two data transfers per clock cycle
Winbond
Winbond
W631GG6KB-15 WINBOND-W631GG6KB-15 Datasheet
3Mb / 158P
   Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Memory Technology Inc.
Elite Semiconductor Mem...
M13L2561616A-2A ESMT-M13L2561616A-2A Datasheet
1Mb / 49P
   Double-data-rate architecture, two data transfers per clock cycle
Winbond
Winbond
W972GG6JB-25 WINBOND-W972GG6JB-25 Datasheet
1Mb / 87P
   Double Data Rate architecture: two data transfers per clock cycle
More results


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz