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W9412G2IB4 Datasheet(PDF) 14 Page - Winbond

Part # W9412G2IB4
Description  Double Data Rate architecture; two data transfers per clock cycle
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
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W9412G2IB4 Datasheet(HTML) 14 Page - Winbond

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W9412G2IB
Publication Release Date: Aug. 30, 2010
- 14 -
Revision A06
7.4 Write Operation
Issuing the Write command after tRCD from the bank activate command. The input data is latched
sequentially, synchronizing with both edges (rising & falling) of DQS after the Write command
(Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode
must be set in the Mode Register at power-up.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated.
When the Write with Auto-precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto-
precharge command cannot be interrupted by any other command for the entire burst data
duration.
Refer to the diagrams for Write operation.
7.5 Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and
Precharge All). When the Bank Precharge command is issued to the active bank, the bank is
precharged and then switched to the idle state. The Bank Precharge command can precharge one
bank independently of the other bank and hold the unprecharged bank in the active state. The
maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each
bank must be precharged within tRAS(max) from the bank activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks
are not in the active state, the Precharge All command can still be issued. In this case, the
Precharge operation is performed only for the active bank and the precharge bank is then
switched to the idle state.
7.6 Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is
terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is
disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write
cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at
which the precharge command is issued. In this case, the DM signal must be asserted “high”
during tWR to prevent writing the invalided data to the cell array.
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst
operation. Refer to the diagrams for Burst termination.
7.7 Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh.
By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh
operation must be performed 4096 times (rows) within 64mS. The period between the Auto
Refresh command and the next command is specified by tRFC.
Self Refresh mode enter issuing the Self Refresh command (CKE asserted “low”), while all banks
are in the idle state. The device is in Self Refresh mode for as long as CKE held “low”. In the case
of distributed Auto Refresh commands, distributed auto refresh commands must be issued every
15.6 µS and the last distributed Auto Refresh commands must be performed within 15.6 µS before
entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation
must be performed within 15.6 µS. In Self Refresh mode, all input/output buffers are disabled,


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