Electronic Components Datasheet Search

Delete All
ON OFF
 ALLDATASHEET.COM Part No.DescriptionMarking X

## W972GG6JB-25 Datasheet(PDF) 52 Page - Winbond

 Part No. W972GG6JB-25 Description Double Data Rate architecture: two data transfers per clock cycle Download 87 Pages Scroll/Zoom 100% Manufacturer WINBOND [Winbond] Direct Link http://www.winbond.com Logo

## W972GG6JB-25 Datasheet(HTML) 52 Page - Winbond

 52 / 87 pageW972GG6JBPublication Release Date: Nov. 29, 2011- 52 -Revision A02-tJIT(duty)tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH fromtCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg).tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}where,tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200}tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200}-tJIT(per), tJIT(per,lck)tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}tJIT(per) defines the single period jitter when the DLL is already locked.tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.-tJIT(cc), tJIT(cc,lck)tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles:tJIT(cc) = Max of |tCKi+1– tCKi|tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.-tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).tERR(nper) = 11nijjtCK–n × tCK(avg)Where50per)–R(11fortER50n1110per)–R(6fortER10n6R(5per)fortER5=nR(4per)fortER4=nR(3per)fortER3=nR(2per)fortER2=n

## Similar Part No. - W972GG6JB-25

 Manufacturer Part No. Datasheet Description Winbond W972GG6JB-18-TR 1Mb / 87P 16M 8 BANKS 16 BIT DDR2 SDRAM
More results

## Similar Description - W972GG6JB-25

 Manufacturer Part No. Datasheet Description Elite Semiconductor Mem... M13S128324A-2M 1Mb / 48P Double-data-rate architecture, two data transfers per clock cycle M13S2561616A-2S 1Mb / 49P Double-data-rate architecture, two data transfers per clock cycle M13S5121632A-2S 705Kb / 48P Double-data-rate architecture, two data transfers per clock cycle Winbond W9412G2IB4 832Kb / 50P Double Data Rate architecture; two data transfers per clock cycle W9412G6JH-5 1Mb / 53P Double Data Rate architecture; two data transfers per clock cycle Elite Semiconductor Mem... M13S2561616A-2A 1Mb / 49P Double-data-rate architecture, two data transfers per clock cycle Winbond W9751G6KB-25 1Mb / 87P Double Data Rate architecture: two data transfers per clock cycle Elite Semiconductor Mem... M13L32321A-2G 1Mb / 48P Double-data-rate architecture, two data transfers per clock cycle Winbond W631GG6KB-15 3Mb / 158P Double Data Rate architecture: two data transfers per clock cycle Elite Semiconductor Mem... M13L2561616A-2A 1Mb / 49P Double-data-rate architecture, two data transfers per clock cycle
More results