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W972GG6JB-25 Datasheet(PDF) 46 Page - Winbond

Part No. W972GG6JB-25
Description  Double Data Rate architecture: two data transfers per clock cycle
Download  87 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W972GG6JB-25 Datasheet(HTML) 46 Page - Winbond

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W972GG6JB
Publication Release Date: Nov. 29, 2011
- 46 -
Revision A02
AC Characteristics and Operating Condition for -25/25I/25A/25K/-3/-3A speed grades, continued
Notes: 1-3 and 45-47 apply to the entire table
SYM.
SPEED GRADE
DDR2-800
(
-25/25I/25A/25K)
DDR2-667
(
-3/-3A)
UNITS
25 NOTES
Bin(CL-tRCD-tRP)
5-5-5/6-6-6
5-5-5
PARAMETER
MIN.
MAX.
MIN.
MAX.
tWPRE
Write preamble
0.35
0.35
tCK(avg)
tWPST
Write postamble
0.4
0.6
0.4
0.6
tCK(avg)
12
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tCK(avg)
14,36
tRPST
Read postamble
0.4
0.6
0.4
0.6
tCK(avg)
14,37
tDS(base) DQ and DM input setup time
50
100
pS
16,27,29,
41,42,44
tDH(base) DQ and DM input hold time
125
175
pS
17,27,29,
41,42,44
tDS(ref)
DQ and DM input setup time
250
300
pS
16,27,29,
41,42,44
tDH(ref)
DQ and DM input hold time
250
300
pS
17,27,29,
41,42,44
tDIPW
DQ and DM input pulse width for each
input
0.35
0.35
tCK(avg)
tHZ
Data-out high-impedance time from
CLK/
CLK
tAC,max
tAC,max
pS
15,35
tLZ(DQS)
DQS/
DQS -low-impedance time from
CLK/
CLK
tAC,min
tAC,max
tAC,min
tAC,max
pS
15,35
tLZ(DQ)
DQ low-impedance time from CLK/
CLK
2 x tAC,min
tAC,max
2 x tAC,min
tAC,max
pS
15,35
tHP
Clock half pulse width
Min.
(tCH(abs),
tCL(abs))
Min.
(tCH(abs),
tCL(abs))
pS
32
tQHS
Data hold skew factor
300
340
pS
33
tQH
DQ/DQS output hold time from DQS
tHP - tQHS
tHP - tQHS
pS
34
tXSNR
Exit Self Refresh to a non-Read command
tRFC + 10
tRFC + 10
nS
23
tXSRD
Exit Self Refresh to a Read command
200
200
nCK
tXP
Exit precharge power down to any
command
2
2
nCK
tXARD
Exit active power down to Read command
2
2
nCK
18
tXARDS
Exit active power down to Read command
(slow exit, lower power)
8 - AL
7 - AL
nCK
18,19
tAOND
ODT turn-on delay
2
2
2
2
nCK
20
tAON
ODT turn-on
tAC,min
tAC,max + 0.7
tAC,min
tAC,max + 0.7
nS
20,35
tAONPD
ODT turn-on (Power Down mode)
tAC,min + 2
2 x tCK(avg) +
tAC,max + 1
tAC,min + 2
2 x tCK(avg) +
tAC,max + 1
nS
tAOFD
ODT turn-off delay
2.5
2.5
2.5
2.5
nCK
21,39
tAOF
ODT turn-off
tAC,min
tAC,max + 0.6
tAC,min
tAC,max + 0.6
nS
21,38,39
tAOFPD
ODT turn-off (Power Down mode)
tAC,min + 2
2.5 x tCK(avg)
+
tAC,max + 1
tAC,min + 2
2.5 x tCK(avg)
+
tAC,max + 1
nS
tANPD
ODT to power down Entry Latency
3
3
nCK
tAXPD
ODT Power Down Exit Latency
8
8
nCK
tMRD
Mode Register Set command cycle time
2
2
nCK
tMOD
MRS command to ODT update delay
0
12
0
12
nS
23
tOIT
OCD Drive mode output delay
0
12
0
12
nS
23
tDELAY
Minimum time clocks remain ON after
CKE asynchronously drops LOW
tIS+tCK(avg)+
tIH
tIS+tCK(avg)+
tIH
nS
22


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