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W631GG6KB-11 Datasheet(PDF) 11 Page - Winbond |
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W631GG6KB-11 Datasheet(HTML) 11 Page - Winbond |
11 / 158 page W631GG6KB Publication Release Date: Feb. 27, 2013 Revision A04 - 11 - 7. FUNCTIONAL DESCRIPTION 7.1 Basic Functionality The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n- bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and continue for a burst len gth of eight or a ‗chopped‘ burst of four in a programmed sequence. Operation begins with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‗on the fly‘ (via A12) if enabled in the mode register. Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation. 7.2 RESET and Initialization Procedure 7.2.1 Power-up Initialization Sequence The following sequence is required for POWER UP and Initialization. 1. Apply power (RESET# is recommended to be maintained below 0.2 * VDD; all other inputs may be undefined). RESET# needs to be maintained for minimum 200 µS with stable power. CKE is pulled ―Low‖ anytime before RESET# being de-asserted (min. time 10 nS). The power voltage ramp time between 300 mV to VDD min. must be no greater than 200 mS; and during the ramp, VDD ≥ VDDQ and (VDD - VDDQ) < 0.3 Volts. VDD and VDDQ are driven from a single power converter output, AND The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95 V max once power ramp is finished, AND VREF tracks VDDQ/2. OR Apply VDD without any slope reversal before or at the same time as VDDQ. Apply VDDQ without any slope reversal before or at the same time as VTT & VREF. The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After RESET# is de-asserted, wait for another 500 µS until CKE becomes active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks. 3. Clocks (CK, CK#) need to be started and stabilized for at least 10 nS or 5 tCK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also, a NOP or Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE is registered ―High‖ after Reset, CKE needs to be continuously registered ―High‖ until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is asserted. Further, the SDRAM keeps its on-die termination in high impedance state after RESET# |
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