W631GG6KB-15 datasheet(3/158 Pages) WINBOND | Double Data Rate architecture: two data transfers per clock cycle

Part No.	W631GG6KB-15

Description	Double Data Rate architecture: two data transfers per clock cycle

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Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

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W631GG6KB

Publication Release Date: Feb. 27, 2013

Revision A04

- 3 -

7.18.1

ZQ Calibration Description ...............................................................................................76

7.18.2

ZQ Calibration Timing ......................................................................................................77

7.18.3

ZQ External Resistor Value, Tolerance, and Capacitive loading......................................77

7.19

On-Die Termination (ODT) ..................................................................................................................78

7.19.1

ODT Mode Register and ODT Truth Table ......................................................................78

7.19.2

Synchronous ODT Mode..................................................................................................79

7.19.2.1

ODT Latency and Posted ODT...............................................................................79

7.19.2.2

Timing Parameters .................................................................................................79

7.19.2.3

ODT during Reads..................................................................................................81

7.19.3

Dynamic ODT ..................................................................................................................82

7.19.3.1

Functional Description: ...........................................................................................82

7.19.3.2

ODT Timing Diagrams ............................................................................................83

7.19.4

Asynchronous ODT Mode ................................................................................................87

7.19.4.1

Synchronous to Asynchronous ODT Mode Transitions ..........................................88

7.19.4.2

Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry ..88

7.19.4.3

Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit.....91

7.19.4.4

Asynchronous to Synchronous ODT Mode during short CKE high and short CKE

low periods

92

8.

OPERATION MODE ...........................................................................................................................93

8.1

Command Truth Table ........................................................................................................................93

8.2

CKE Truth Table .................................................................................................................................95

8.3

Simplified State Diagram.....................................................................................................................96

9.

ELECTRICAL CHARACTERISTICS ...................................................................................................97

9.1

Absolute Maximum Ratings.................................................................................................................97

9.2

Operating Temperature Condition.......................................................................................................97

9.3

DC & AC Operating Conditions ...........................................................................................................98

9.3.1

Recommended DC Operating Conditions ........................................................................98

9.4

Input and Output Leakage Currents ....................................................................................................98

9.5

Interface Test Conditions ....................................................................................................................98

9.6

DC and AC Input Measurement Levels ...............................................................................................99

9.6.1

DC and AC Input Levels for Single-Ended Command and Address Signals ....................99

9.6.2

DC and AC Input Levels for Single-Ended Data Signals................................................100

9.6.3

Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ...........102

9.6.4

Single-ended requirements for differential signals .........................................................103

9.6.5

Differential Input Cross Point Voltage ............................................................................104

9.6.6

Slew Rate Definitions for Single-Ended Input Signals....................................................105

9.6.7

Slew Rate Definitions for Differential Input Signals ........................................................105

9.7

DC and AC Output Measurement Levels ..........................................................................................106

9.7.1

Output Slew Rate Definition and Requirements .............................................................106

9.7.1.1

Single Ended Output Slew Rate ...........................................................................107

9.7.1.2

Differential Output Slew Rate ...............................................................................108

9.8

34 ohm Output Driver DC Electrical Characteristics..........................................................................109

9.8.1

Output Driver Temperature and Voltage sensitivity........................................................111

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