W631GG6KB-15 datasheet(59/158 Pages) WINBOND

Part #	W631GG6KB-15

Description	Double Data Rate architecture: two data transfers per clock cycle

Download	158 Pages

Scroll/Zoom	100%

Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

Logo

59 / 158 page

W631GG6KB

Publication Release Date: Feb. 27, 2013

Revision A04

- 59 -

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Tn

CK#

CK

Command*3

Address*4

DQS, DQS#

DQ*2

Din

n

Din

n+2

Din

n+3

Bank

Col n

WRITE

NOP

READ

WL = 5

tWPRE

Din

n+1

tWPST

NOP

tWTR*5

Bank

Col b

RL = 6

TIME BREAK

TRANSITIONING DATA

DON'T CARE

Notes:

1. BC4, WL = 5, RL = 6.

2. Din n = data-in from column n; Dout b = data-out from column b.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0 and READ command at Tn.

5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data

shown at T7.

Figure 45

– WRITE (BC4) to READ (BC4) Operation

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Tn

CK#

CK

Command*3

Address*4

DQS, DQS#

DQ*2

Din

n

Din

n+2

Din

n+3

Bank

Col n

WRITE

NOP

PRE

WL = 5

tWPRE

Din

n+1

tWPST

NOP

tWR*5

TIME BREAK

TRANSITIONING DATA

DON'T CARE

Notes:

1. BC4, WL = 5, RL = 6.

2. Din n = data-in from column n; Dout b = data-out from column b.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0.

5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7. tWR specifies

the last burst write cycle until the precharge command can be issued to the same bank.

Figure 46

– WRITE (BC4) to PRECHARGE Operation

Similar Part No. - W631GG6KB-15

Manufacturer	Part #	Datasheet	Description
Winbond	W631GU6KB-12-TR	4Mb / 160P	8M ??8 BANKS ??16 BIT DDR3L SDRAM

More results

Similar Description - W631GG6KB-15

Manufacturer	Part #	Datasheet	Description
Elite Semiconductor Mem...	M13S128324A-2M	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S5121632A-2S	705Kb / 48P	Double-data-rate architecture, two data transfers per clock cycle
	M13S2561616A-2S	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9412G2IB4	832Kb / 50P	Double Data Rate architecture; two data transfers per clock cycle
Winbond	W9412G6JH-5	1Mb / 53P	Double Data Rate architecture; two data transfers per clock cycle
Elite Semiconductor Mem...	M13S2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W9751G6KB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle
Elite Semiconductor Mem...	M13L32321A-2G	1Mb / 48P	Double-data-rate architecture, two data transfers per clock cycle
Elite Semiconductor Mem...	M13L2561616A-2A	1Mb / 49P	Double-data-rate architecture, two data transfers per clock cycle
Winbond	W972GG6JB-25	1Mb / 87P	Double Data Rate architecture: two data transfers per clock cycle

More results

W631GG6KB-15 Datasheet(PDF) 59 Page - Winbond

W631GG6KB-15 Datasheet(HTML) 59 Page - Winbond

Similar Part No. - W631GG6KB-15

Similar Description - W631GG6KB-15

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL