W631GG6KB-15 datasheet(42/158 Pages) WINBOND

Part #	W631GG6KB-15

Description	Double Data Rate architecture: two data transfers per clock cycle

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W631GG6KB

Publication Release Date: Feb. 27, 2013

Revision A04

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7.13 READ Operation

7.13.1 READ Burst Operation

During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12

during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled).

A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)

A12 = 1, BL8

A12 is used only for burst length control, not as a column address.

TRANSITIONING DATA

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

CK#

CK

Command*

3

READ

Address*

4

NOP

Bank

Col n

DON'T CARE

DQS, DQS#

DQ*

2

CL = 6

Dout

n

Dout

n+1

RL = AL + CL

tRPRE

Dout

n+2

Dout

n+3

Dout

n+4

Dout

n+5

Dout

n+6

Dout

n+7

tRPST

NOP

Notes:

1. BL8, RL = 6, AL = 0, CL = 6.

2. Dout n = data-out from column n.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.

Figure 21

– READ Burst Operation RL = 6 (AL = 0, CL = 6, BL8)

TRANSITIONING DATA

T0

T1

T5

T6

T10

T11

T12

T13

T14

T15

T16

CK#

CK

Command*

3

READ

Address*

4

NOP

Bank

Col n

DON'T CARE

DQS, DQS#

DQ*

2

CL = 6

Dout

n

Dout

n+1

RL = AL + CL

tRPRE

Dout

n+2

Dout

n+3

Dout

n+4

Dout

n+5

Dout

n+6

Dout

n+7

tRPST

NOP

AL = 5

TIME BREAK

Notes:

1. BL8, RL = 11, AL = (CL - 1), CL = 6.

2. Dout n = data-out from column n.

3. NOP commands are shown for ease of illustration; other commands may be valid at these times.

4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.

Figure 22

– READ Burst Operation RL = 11 (AL = 5, CL = 6, BL8)

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