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W631GG6KB-15 Datasheet(PDF) 4 Page - Winbond

Part # W631GG6KB-15
Description  Double Data Rate architecture: two data transfers per clock cycle
Download  158 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W631GG6KB-15 Datasheet(HTML) 4 Page - Winbond

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W631GG6KB
Publication Release Date: Feb. 27, 2013
Revision A04
- 4 -
9.9
On-Die Termination (ODT) Levels and Characteristics .....................................................................112
9.9.1
ODT Levels and I-V Characteristics ...............................................................................112
9.9.2
ODT DC Electrical Characteristics .................................................................................113
9.9.3
ODT Temperature and Voltage sensitivity .....................................................................113
9.9.4
Design guide lines for RTTPU and RTTPD .......................................................................114
9.10
ODT Timing Definitions .....................................................................................................................115
9.10.1
Test Load for ODT Timings ............................................................................................115
9.10.2
ODT Timing Definitions ..................................................................................................115
9.11
Input/Output Capacitance .................................................................................................................119
9.12
Overshoot and Undershoot Specifications ........................................................................................120
9.12.1
AC Overshoot /Undershoot Specification for Address and Control Pins: .......................120
9.12.2
AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins:.........120
9.13
IDD and IDDQ Specification Parameters and Test Conditions .........................................................121
9.13.1
IDD and IDDQ Measurement Conditions .......................................................................121
9.13.2
IDD Current Specifications .............................................................................................131
9.14
Clock Specification............................................................................................................................132
9.15
Speed Bins........................................................................................................................................133
9.15.1
DDR3-1333 Speed Bin and Operating Conditions .........................................................133
9.15.2
DDR3-1600 Speed Bin and Operating Conditions .........................................................134
9.15.3
DDR3-1866 Speed Bin and Operating Conditions .........................................................135
9.15.4
Speed Bin General Notes ..............................................................................................136
9.16
AC Characteristics ............................................................................................................................137
9.16.1
AC Timing and Operating Condition for -11 speed grade ..............................................137
9.16.2
AC Timing and Operating Condition for -12/12I/12A/12K/-15/15I/15A/15K speed grades
141
9.16.3
Timing Parameter Notes ................................................................................................145
9.16.4
Address / Command Setup, Hold and Derating .............................................................148
9.16.5
Data Setup, Hold and Slew Rate Derating .....................................................................155
10.
PACKAGE SPECIFICATION ............................................................................................................157
11.
REVISION HISTORY ........................................................................................................................158


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