ADS7891

SLAS410 − DECEMBER 2003

www.ti.com

5

TIMING REQUIREMENTS

All specifications typical at −40

°C to 85°C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, 3, and 4)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

REF FIG.

Conversion time

t(conv)

255

273

ns

5

Acquisition time

t(acq)

60

78

ns

5

SAMPLING AND CONVERSION START

Hold time CS low to CONVST high (with BUSY high)

th1

10

ns

3

Delay CONVST high to acquisition start

td1

2

4

5

ns

1

Hold time, CONVST high to CS high with BUSY low

th2

10

ns

1

Hold time, CONVST low to CS high

th3

10

ns

1

Delay CONVST low to BUSY high

td2

40

ns

1

CS width for acquisition or conversion to start

tw3

20

ns

2

Delay CS low to acquisition start with CONVST high

td3

2

4

5

ns

2

Pulse width, from CS low to CONVST low for acquisition to start

tw1

20

ns

2

Delay CS low to BUSY high with CONVST low

td4

40

ns

2

Quiet sampling time(3)

25

ns

CONVERSION ABORT

Setup time CONVST high to CS low with BUSY high

tsu1

15

ns

4

Delay time CS low to BUSY low with CONVST high

td5

20

ns

4

DATA READ

Delay RD low to data valid with CS low

td6

25

ns

5

Delay BYTE high to LSB word valid with CS and RD low

td7

25

ns

5

Delay time RD high to data 3-state with CS low

td9

25

ns

5

Delay time end of conversion to BUSY low

td11

20

ns

5

Quiet sampling time RD high to CONVST low

t1

25

ns

5

Delay CS low to data valid with RD low

td8

25

ns

6

Delay CS high to data 3-state with RD low

td10

25

ns

6

Quiet sampling time CS low to CONVST low

t2

25

ns

6

BACK-TO-BACK CONVERSION

Delay BUSY low to data valid

td12

10

ns

7, 8

Pulse width, CONVST high

tw4

70

ns

7, 8

Pulse width, CONVST low

tw5

20

ns

7

POWER DOWN/RESET

Pulse width, low for PWD/RST to reset the device

tw6

45

6140

ns

12

Pulse width, low for PWD/RST to power down the device

tw7

7200

ns

11

Delay time, power up after PWD/RST is high

td13

25

ms

11

(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.

(2) See timing diagram.

(3) Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period.

(4) All timings are measured with 20 pF equivalent loads with 5 V +VBD and 10-pF equivalent loads with 3 V +VBD on all data bits and BUSY pin.