FAN4822

PRODUCT SPECIFICATION

6

REV. 1.0.1 8/10/01

Functional Description

Switching losses of wide input voltage range PFC boost con-

verters increase dramatically as power levels increase above

200 watts. The use of zero-voltage switching (ZVS) tech-

niques improves the efficiency of high power PFCs by sig-

nificantly reducing the turn-on losses of the boost MOSFET.

ZVS is accomplished by using a second, smaller MOSFET,

together with a storage element (inductor) to convert the

turn-on losses of the boost MOSFET into useful output

power.

The basic function of the FAN4822 is to provide a power

factor corrected, regulated DC bus voltage using continuous,

average current-mode control. Like Micro Linear’s family of

PFC/PWM controllers, the FAN4822 employs leading-edge

pulse width modulation to reduce system noise and permit

frequency synchronization to a trailing edge PWM stage for

the highest possible DC bus voltage bandwidth. For minimi-

zation of switching losses, circuitry has been incorporated to

control the switching of the ZVS FET.

Theory of Operation

Figure 1 shows a simplified schematic of the output and con-

trol sections of a high power PFC circuit. Figure 2 shows the

relationship of various waveforms in the circuit. Q1 func-

tions as the main switching FET and Q2 provides the ZVS

action. During each cycle, Q2 turns on before Q1, diverting

the current in L1 away from D1 into L2. The current in L2

When these currents are equal, L1 ceases discharging current

voltage of Q1 begins to fall. The shape of the voltage wave-

form is sinusoidal due to the interaction of L2 and the com-

bined parasitic capacitance of D1 and Q1 (or optional ZVS

low that the controller turns Q2 off and Q1 on. Q1 then

behaves as an ordinary PFC switch, storing energy in the

boost inductor L1. The energy stored in L2 is completely dis-

charged into the boost capacitor via D2 during the Q1 off-

time and the value of L2 must be selected for discontinuous-

mode operation.

Component Selection

Q1 Turn-Off

Because the FAN4822 uses leading edge modulation, the

PFC MOSFET (Q1) is always turned off at the end of each

oscillator ramp cycle. For proper operation, the internal ZVS

flip-flop must be reset every cycle during the oscillator dis-

charge time. This is done by automatically resetting the ZVS

comparator a short time after the drain voltage of the main Q

has reached zero (refer to Figure 1 sense circuit). This sense

circuit terminates the ZVS on time by sensing the main Q

drain voltage reaching zero. It is then reset by way of a resis-

the ZVS comparator is not reset at the main Q turn off which

occurs at the end of the clock cycle. This avoids the potential

for improper reset of the internal ZVS flip-flop.

Another concern is the proper operation of the ZVS compar-

ator during discontinuous mode operation (DCM), which

will occur at the cusps of the rectified AC waveform and at

light loads. Due to the nature of the voltage seen at the drain

of the main boost Q during DCM operation, the ZVS com-

parator can be fooled into forcing the ZVS Q on for the

entire period. By adding a circuit which limits the maximum

on time of the ZVS Q, this problem can be avoided. Q3 in

Figure 1 provides this function.

Figure 1. Simplified PFC/ZVS Schematic.

11

10

9

8

7

12

C3

33pF

C4

330pF

C5

C1

C2

D1

D2

L1

+

Q1

Q3

Q2

R1

PFC OUT

ZVS OUT

PWR GND

ZV SENSE

GND

FAN4822

MAX ZVS

ON TIME LIMIT

L2

R6

22k

R3

22k

R2

R4

51k

R5

220