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DM93L28 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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DM93L28 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 5 page ![]() © 1999 Fairchild Semiconductor Corporation DS010200 www.fairchildsemi.com March 1989 Revised August 1999 DM93L28 Dual 8-Bit Shift Register General Description The DM93L28 is a high speed serial storage element pro- viding 16 bits of storage in the form of two 8-bit registers. The multifunctional capability of this device is provided by several features: 1) additional gating is provided at the input to both shift registers so that the input is easily multi- plexed between two sources; 2) the clock of each register may be provided separately or together; 3) both the true and complementary outputs are provided from each 8-bit register, and both registers may be master cleared from a common input. Features s 2-input multiplexer provided at data input of each register s Gated clock input circuitry s Both true and complementary outputs provided from last bit of each register s Asynchronous master reset common to both registers Ordering Code: Logic Symbol VCC = Pin 16 GND = Pin 8 Connection Diagram Pin Descriptions Order Number Package Number Package Description DM93L28N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description S Data Select Input D0, D1 Data Inputs CP Clock Pulse Input (Active HIGH) Common (Pin 9) Separate (Pins 7 and 10) MR Master Reset Input (Active LOW) Q7 Last Stage Output Q7 Complementary Output |