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DM9374 Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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DM9374 Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 8 page 3 www.fairchildsemi.com Functional Description The DM9374 is a 7-segment decoder/driver with latches on the address inputs and active LOW constant current out- puts to drive LEDs directly. This device accepts a 4-bit binary code and produces output drive to the appropriate segments of the 7-segment display. It has a decode format which produces numeric codes “0” through “9” and other codes. Latches on the four data inputs are controlled by an active LOW Latch Enable, LE. When LE is LOW, the state of the outputs is determined by the input data. When LE goes HIGH, the last data present at the inputs is stored in the latches and the outputs remain stable. The LE pulse width necessary to accept and store data is typically 50 ns, which allows data to be strobed into the DM9374 at normal TTL speeds. This feature means that data can be routed directly from high speed counters and frequency dividers into the display without slowing down the system clock or providing intermediate data storage. The latch/decoder combination is a simple system which drives LED displays with multiplexed data inputs from MOS time clocks, DVMs, calculator chips, etc. Data inputs are multiplexed while the displays are in static mode. This low- ers component and insertion costs, since several circuits— seven resistors per display, strobe drivers, a separate dis- play voltage source, and clock failure detect circuits—tradi- tionally found in multiplexed display systems are eliminated. It also allows low strobing rates to be used with- out display flicker. Another DM9374 feature is the reduced loading on the data inputs when the Latch Enable is HIGH (only 10 µA typ). This allows many DM9374s to be driven from a MOS device in multiplex mode without the need for drivers on the data lines. The DM9374 also provides automatic blank- ing of the leading and/or trailing-edge zeroes in a multidigit decimal number, resulting in an easily readable decimal display conforming to normal writing practice. In an 8-digit mixed integer fraction decimal representation, using the automatic blanking capability 0060.0300 would be dis- played as 60.03. Leading-edge zero suppression is obtained by connecting the Ripple Blanking Output (RBO) of a decoder to the Ripple Blanking Input (RBI) of the next lower stage device. The most significant decoder stage should have the RIB input grounded; and since suppres- sion of the least significant integer zero in a number is not usually desired, the RBI input of this decoder stage should be left open. A similar procedure for the fractional part of a display will provide automatic suppression of trailing-edge zeroes. The RBO terminal of the decoder can be OR-tied with a modulating signal via an isolating buffer to achieve duration intensity modulation. A suitable signal can be gen- erated for this purpose by forming a variable frequency multivibrator with a cross coupled pair of TTL or DTL gates. Logic Diagram |
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