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DM74S74 Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part No. DM74S74
Description  Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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DM74S74 Datasheet(HTML) 3 Page - Fairchild Semiconductor

   
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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Clear is tested with preset HIGH and preset is tested with clear HIGH.
Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 8: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 5)
VI
Input Clamp Voltage
VCC = Min, II = − 18 mA
−1.2
V
VOH
HIGH Level
VCC = Min, IOH = Max
2.7
3.4
V
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
0.5
V
Output Voltage
VIH = Min, VIL = Max
II
Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
1
mA
IIH
HIGH Level
VCC = Max
D
50
Input Current
VI = 2.7V
Clear
150
µA
Preset
100
Clock
100
IIL
LOW Level
VCC = Max
D
−2
Input Current
VI = 0.5V
Clear
−6
mA
(Note 6)
Preset
−4
Clock
−4
IOS
Short Circuit Output Current
VCC = Max (Note 7)
−40
−100
mA
ICC
Supply Current
VCC = Max, (Note 8)
30
50
mA
RL = 280Ω
Symbol
Parameter
From (Input)
CL = 15 pF
CL = 50 pF
Units
To (Output)
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
75
65
MHz
tPLH
Propagation Delay Time
Preset to Q
6
9
ns
LOW-to-HIGH Level Output
tPLH
Propagation Delay Time
Clear to Q
69
ns
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Preset to Q
13.5
17
ns
HIGH-to-LOW Level Output
(Clock HIGH)
tPHL
Propagation Delay Time
Preset to Q
814
ns
HIGH-to-LOW Level Output
(Clock LOW)
tPHL
Propagation Delay Time
Clear to Q
13.5
16
ns
HIGH-to-LOW Level Output
(Clock HIGH)
tPHL
Propagation Delay Time
Clear to Q
8
13
ns
HIGH-to-LOW Level Output
(Clock LOW)
tPLH
Propagation Delay Time
Clock to Q or Q
912
ns
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Clock to Q or Q
914
ns
HIGH-to-LOW Level Output


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