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DM74S112 Datasheet(PDF) 2 Page - Fairchild Semiconductor

Part No. DM74S112
Description  Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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DM74S112 Datasheet(HTML) 2 Page - Fairchild Semiconductor

   
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2
Absolute Maximum Ratings(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 2: CL = 15 pF, RL = 280Ω, TA = 25°C and VCC = 5V.
Note 3: CL = 50 pF, RL = 280Ω, TA = 25°C and VCC = 5V.
Note 4: TA = 25°C and VCC = 5V.
Note 5: The symbol (
↓) indicates the falling edge at the clock pulse is used for reference.
Supply Voltage
7V
Input Voltage
5.5V
Operating Free Air Temperature Range
0
°C to +70°C
Storage Temperature Range
−65°C to +150°C
Symbol
Parameter
Min
Nom
Max
Units
VCC
Supply Voltage
4.75
5
5.25
V
VIH
HIGH Level Input Voltage
2
V
VIL
LOW Level Input Voltage
0.8
V
IOH
HIGH Level Output Current
−1mA
IOL
LOW Level Output Current
20
mA
fCLK
Clock Frequency (Note 2)
0
125
80
MHz
fCLK
Clock Frequency (Note 3)
0
80
60
MHz
tW
Pulse Width
Clock HIGH
6
(Note 2)
Clock LOW
6.5
ns
Clear LOW
8
Preset LOW
8
tW
Pulse Width
Clock HIGH
8
(Note 3)
Clock LOW
8
ns
Clear LOW
10
Preset LOW
10
tSU
Setup Time (Note 4)(Note 5)
7
ns
tH
Input Hold Time (Note 4)(Note 5)
0
ns
TA
Free Air Operating Temperature
0
70
°C


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