© 2000 Fairchild Semiconductor Corporation

DS006372

www.fairchildsemi.com

August 1986

Revised March 2000

DM74LS73A

Dual Negative-Edge-Triggered Master-Slave

J-K Flip-Flops with Clear and Complementary Outputs

General Description

This device contains two independent negative-edge-trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flops on the falling edge of

the clock pulse. The clock triggering occurs at a voltage

level and is not directly related to the transition time of the

negative going edge of the clock pulse. The data on the J

and K inputs is allowed to change while the clock is HIGH

or LOW without affecting the outputs as long as setup and

hold times are not violated. A low logic level on the clear

input will reset the outputs regardless of the levels of the

other inputs.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

H

= HIGH Logic Level

L

= LOW Logic Level

X

= Either LOW or HIGH Logic Level

↓ = Negative going edge of pulse.

established.

Toggle

= Each output changes to the complement of its previous level on

each falling edge of the clock pulse.

Order Number

Package Number

Package Description

DM74LS73AM

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS73AN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Outputs

CLR

CLK

J

K

Q

Q

LX

X

X

L

H

H

↓

LL

H

↓

HL

H

L

H

↓

LH

L

H

H

↓

H

H

Toggle

HH

X

X