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DM74LS74A Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part No. DM74LS74A
Description  Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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DM74LS74A Datasheet(HTML) 3 Page - Fairchild Semiconductor

   
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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 7: All typicals are at VCC = 5V, TA = 25°C.
Note 8: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum
and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 9: With all outputs OPEN, ICC is measured with CLOCK grounded after setting the Q and Q outputs HIGH in turn.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 7)
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
−1.5
V
VOH
HIGH Level
VCC = Min, IOH = Max
2.7
3.4
V
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
0.35
0.5
Output Voltage
VIL = Max, VIH = Min
V
IOL = 4 mA, VCC = Min
0.25
0.4
II
Input Current @ Max
VCC = Max
Data
0.1
Input Voltage
VI = 7V
Clock
0.1
mA
Preset
0.2
Clear
0.2
IIH
HIGH Level
VCC = Max
Data
20
Input Current
VI = 2.7V
Clock
20
µA
Clear
40
Preset
40
IIL
LOW Level
VCC = Max
Data
−0.4
Input Current
VI = 0.4V
Clock
−0.4
mA
Preset
−0.8
Clear
−0.8
IOS
Short Circuit Output Current
VCC = Max (Note 8)
−20
−100
mA
ICC
Supply Current
VCC = Max (Note 9)
4
8
mA
From (Input)
RL = 2 kΩ
Symbol
Parameter
To (Output)
CL = 15 pF
CL = 50 pF
Units
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
25
20
MHz
tPLH
Propagation Delay Time
Clock to Q or Q
25
35
ns
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Clock to Q or Q
30
35
ns
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
Preset to Q
25
35
ns
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Preset to Q
30
35
ns
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
Clear to Q
25
35
ns
LOW-to-HIGH Level Output
tPHL
Propagation Delay Time
Clear to Q
30
35
ns
HIGH-to-LOW Level Output


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