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DM74LS73A Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part No. DM74LS73A
Description  Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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DM74LS73A Datasheet(HTML) 3 Page - Fairchild Semiconductor

   
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Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 5: All typicals are at VCC = 5V, TA = 25°C.
Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,
where shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where VO = 2.125V with the mini-
mum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.
Note 7: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement, the clock is grounded.
Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 5)
VI
Input Clamp Voltage
VCC = Min, II = −18 mA
−1.5
V
VOH
HIGH Level
VCC = Min, IOH = Max
2.7
3.4
V
Output Voltage
VIL = Max, VIH = Min
VOL
LOW Level
VCC = Min, IOL = Max
0.35
0.5
Output Voltage
VIL = Max, VIH = Min
V
IOL = 4 mA, VCC = Min
0.25
0.4
II
Input Current @ Max
VCC = Max
J, K
0.1
Input Voltage
VI = 7V
Clear
0.3
mA
Clock
0.4
IIH
HIGH Level
VCC = Max
J, K
20
Input Current
VI = 2.7V
Clear
60
µA
Clock
80
IIL
LOW Level
VCC = Max
J, K
−0.4
Input Current
VI = 0.4V
Clear
−0.8
mA
Clock
−0.8
IOS
Short Circuit Output Current
VCC = Max (Note 6)
−20
−100
mA
ICC
Supply Current
VCC = Max (Note 7)
4
6
mA
From (Input)
RL = 2 kΩ
Symbol
Parameter
To (Output)
CL = 15 pF
CL = 50 pF
Units
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
30
25
MHz
tPHL
Propagation Delay Time
Clear
20
28
ns
HIGH-to-LOW Level Output
to Q
tPLH
Propagation Delay Time
Clear
20
24
ns
LOW-to-HIGH Level Output
to Q
tPLH
Propagation Delay Time
Clock to
20
24
ns
LOW-to-HIGH Level Output
Q or Q
tPHL
Propagation Delay Time
Clock to
20
28
ns
HIGH-to-LOW Level Output
Q or Q


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