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AT89LP51ED2-20JU Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT89LP51ED2-20JU Datasheet(HTML) 4 Page - ATMEL Corporation |
4 / 26 page 4 3714AS–MICRO–7/11 AT89LP51RD2/ED2/ID2 Summary - Preliminary 16 22 20 GND I Ground 17 23 P4.3 I/O I/O P4.3: User-configurable I/O Port 4bit 3. DDA: Bidirectional Debug Data line for the On-Chip Debug Interface when OCD is enabled. 18 24 21 P2.0 I/O O P2.0: User-configurable I/O Port 2 bit 0. A8: External memory interface Address bit 8. 19 25 22 P2.1 I/O O P2.1: User-configurable I/O Port 2 bit 1. A9: External memory interface Address bit 9. 20 26 23 P2.1 I/O O O P2.2: User-configurable I/O Port 2 bit 2. DA-: DAC negative differential output. A10: External memory interface Address bit 10. 21 27 24 P2.3 I/O O O P2.3: User-configurable I/O Port 2 bit 3. DA+-: DAC positive differential output. A11: External memory interface Address bit 11. 22 28 25 P2.4 I/O I O P2.4: User-configurable I/O Port 2 bit 5. AIN0: Analog Comparator Input 0. A12: External memory interface Address bit 12. 23 29 26 P2.5 I/O I O P2.5: User-configurable I/O Port 2 bit 5. AIN1: Analog Comparator Input 1. A13: External memory interface Address bit 13. 24 30 27 P2.6 I/O I O P2.6: User-configurable I/O Port 2 bit 6. AIN2: Analog Comparator Input 2. A14: External memory interface Address bit 14. 25 31 28 P2.7 I/O I O P2.7: User-configurable I/O Port 2 bit 7. AIN3: Analog Comparator Input 3. A15: External memory interface Address bit 15. 26 32 29 P4.5 I/O O P4.5: User-configurable I/O Port 4 bit 5. PSEN: External memory interface Program Store Enable (active-low). 27 33 30 P4.4 I/O I/O P4.4: User-configurable I/O Port 4 bit 4. ALE: External memory interface Address Latch Enable. 28 34 P4.0 I/O P4.0: User-configurable I/O Port 4 bit 0. SCL: TWI Serial Clock line. This line is an output in mater mode and an input in slave mode. 29 35 31 POL I POL: Reset polarity 30 36 32 P0.7 I/O I/O P0.7: User-configurable I/O Port 0 bit 7. AD7: External memory interface Address/Data bit 7. 31 37 33 P0.6 I/O I/O I P0.6: User-configurable I/O Port 0 bit 6. AD6: External memory interface Address/Data bit 6. ADC6: ADC analog input 6. 32 38 34 P0.5 I/O I/O I P0.5: User-configurable I/O Port 0 bit 5. AD5: External memory interface Address/Data bit 5. ADC5: ADC analog input 5. 33 39 35 P0.4 I/O I/O I P0.4: User-configurable I/O Port 0 bit 4. AD4: External memory interface Address/Data bit 4. ADC4: ADC analog input 4. 34 40 36 P0.3 I/O I/O I P0.3: User-configurable I/O Port 0 bit 3. AD3: External memory interface Address/Data bit 3. ADC3: ADC analog input 3. Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description Pin Number Symbol Type Description VQFP VQFN PLCC (1) PDIP |
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