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AT30TSE754-XM8-T Datasheet(PDF) 30 Page - ATMEL Corporation |
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AT30TSE754-XM8-T Datasheet(HTML) 30 Page - ATMEL Corporation |
30 / 60 page 30 Atmel AT30TSE752/754/758 [DATASHEET] 8751D–DTS–8/2012 After the Master has issued a Stop condition, the AT30TSE752/754/758 will begin the internally self-timed program operation, and the contents of the Nonvolatile TLOW or THIGH Limit Register will be updated within a time of tPROG. During this time, the NVRBSY bit of the Configuration Register will indicate that the device is busy. If the Master issues a repeated Start condition instead of a Stop condition, the AT30TSE752/754/758 will abort the operation and the contents of the Nonvolatile TLOW or THIGH Limit Register will not be changed.. In addition to the Master not sending two complete bytes of data, writing to the Nonvolatile TLOW or THIGH Limit Register will be ignored and no operation will be performed under the following conditions: the Nonvolatile Registers are already busy (the NVRBSY bit of the Configuration Register is in the Logic 1 state), the Volatile and Nonvolatile Registers are currently locked (the RLCK bit of the Nonvolatile Configuration Register is in the Logic 1 state), or the Volatile and Nonvolatile Registers are permanently locked down (the RLCKDWN bit of the Nonvolatile Configuration Register is in the Logic 1 state). However, the device will still respond with an ACK, except in the case of the Nonvolatile Registers being busy, to indicate that it received the proper data bytes even though the program operation will not be performed. In the case of the Nonvolatile Registers being busy, the device will respond with an ACK to the address and pointer bytes but will then NACK when the data bytes are sent from the Master. In order to read the Nonvolatile TLOW or THIGH Limit Register, the Pointer Register must be set or have been previously set to 12h to select the Nonvolatile TLOW Limit Register or 13h to select the Nonvolatile THIGH Limit Register (if the previous operation was a Write to one of the registers, then the Pointer Register will already be set for that particular limit register). If the Pointer Register has already been set appropriately, the Nonvolatile TLOW or THIGH Limit Register can be read by having the Master first initiate a Start condition followed by the AT30TSE752/754/758 device address byte (1001AAA1 where “AAA” corresponds to the hard-wired A2-0 address pins). After the AT30TSE752/754/758 has received the proper address byte, the device will send an ACK to the Master. The Master can then read the upper byte of the Nonvolatile TLOW or THIGH Limit Register. After the upper byte of the register has been clocked out of the AT30TSE752/754/758, the Master must send an ACK to indicate that it is ready for the lower byte of data. The AT30TSE752/754/758 will then clock out the lower byte of the register, after which the Master must send a NACK to end the operation. When the AT30TSE752/754/758 receives the NACK, it will release the SDA line so that the Master can send a Stop or repeated Start condition. If the Master does not send a NACK but instead sends an ACK after the lower byte of the register has been clocked out, then invalid data will be output by the device. The Nonvolatile TLOW Limit Register is factory-set to default to 4B00h (+75C) and the Nonvolatile THIGH Limit Register is set to default to 5000h (+80 C); therefore, both registers will need to be modified if these default temperature limits are not satisfactory for the application. Figure 6-10. Write to Nonvolatile TLOW or THIGH Limit Register SCL SDA Start by Master ACK from Slave ACK from Slave Address Byte Nonvolatile T LOW or THIGH Limit Register Upper Byte Nonvolatile T LOW or THIGH Limit Register Lower Byte Pointer Register Byte MSB MSB ACK from Slave ACK from Slave Stop by Master MSB MSB 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 A A A 0 0 0 0 0 1 0 0 P1 P0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 0 |
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