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DM74LS373 Datasheet(PDF) 1 Page - Fairchild Semiconductor

Part No. DM74LS373
Description  3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
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Maker  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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DM74LS373 Datasheet(HTML) 1 Page - Fairchild Semiconductor

   
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© 2000 Fairchild Semiconductor Corporation
DS006431
www.fairchildsemi.com
April 1986
Revised March 2000
DM74LS373 • DM74LS374
3-STATE Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74LS373 are transparent D-
type latches meaning that while the enable (G) is HIGH the
Q outputs will follow the data (D) inputs. When the enable
is taken LOW the output will be latched at the level of the
data that was set up.
The eight flip-flops of the DM74LS374 are edge-triggered
D-type flip flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs
are OFF.
Features
s Choice of 8 latches or 8 D-type flip-flops in a single
package
s 3-STATE bus-driving outputs
s Full parallel-access for loading
s Buffered control inputs
s P-N-P inputs reduce D-C loading on data lines
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
Package Number
Package Description
DM74LS373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS374WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS374SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
IDM29901NC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide


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